CS/EE 3710 - Computer Design Lab
Fall 2008

• Labs and checkpoints: 35%
• Mid-semester presenation: 10%
• Final Project: 45%
  • Written Documentation: 20%
  • Project details: 35%
• Final Exam: 10%

Assignments / Labs

1. Review Assignment: This assignment will cover material that I think you should have learned in CS/EE 3700 and CS/EE 3810. If you can't remember this stuff, these are the areas where you need to refresh your memory. If you have no idea about this stuff, you'll struggle in the class! Due Thursday, September 4th at 5:00 (hand in during class).
   
   
2. Finite State Machine Lab: Tbird Turn Signals mapped to the Spartan-3E board. This is the same Tbird assignment as last semester in 3700, but mapped to the Spartan-3E board. Check out the tutorial on using ISE 10.1 with the Spartan-3E board. There are other tutorials on the CS/EE 3700 web site too. Due Thursday, September 11th, 5:00pm.
   
   
3. Tiny MIPS processor: In this lab you'll use the mips.v code from CMOS VLSI Design by Weste and Harris. I'll also give you exmem.v which is Verilog code that describes memory that can be implemented as block RAM on the Spartan-3E part. Finally, I'll give you fibn.asm, an assembly program that computes the n-th Fibonacci number, and the corresponding fib.dat file with the machine encoded version that you can use to load the Block RAM. The details of this MIPS process are found in Section 1.7 of CMOS VLSI Design. I've handed out hard copies of that section in class. Due Tuesday, September 23rd, 5:00pm.
   
   You'll have to modify things in three ways (as described in the upcoming lab handout)
   1. Add an add-immediate (ADDI) instruction to the processor
   2. Add simple memory-mapped I/O to the switches and LEDs of the Spartan-3E board
   3. Write a new Fibonacci program that computes the first 14 numbers (starting at 0), stores them in memory, and then retrieves those numbers using the switches and LEDs
   4. Demonstrate the new Fibonacci code running on the Spartan-3E board
   
   
4. Forming Groups: Here is a form you can use to tell us who is in your group. Due Tuesday, September 23rd, 5:00pm.
   You can send this in by email also to teach-3710@list.eng.utah.edu
   
   
5. Checkpoints: From here on out you'll be working in groups on your processor projects. We'll schedule group meetings with each group to monitor your progress. You'll need to check off a series of checkpoints to demonstrate that progress. I haven't put a specific schedule on these checkpoint so that your group can set your own timetable, but if you start falling behind I may put specific time tables in place on a per-group basis.

   At a couple places in the semester we'll also schedule in-class presentations by each group about their project. There will be one such presentation in mid October, and another late November.

• Checkpoint #1: In this checkpoint you'll document your register file and ALU. Details can be found here.
• Checkpoint #2: In this checkpoint you'll document your complete datapath including a connection to Block RAM, some very basic memory mapped I/O, and a plan for your final memory solution. Details can be found here.
• Checkpoint #3: In this checkpoint you'll demonstrate your instruction decoding and how it interacts with your datapath. Details TBA.
• Checkpoint #4: In this checkpoint you'll document your control finite state machine that is controlling everything. At this point you should be able to demonstrate code running on your processor. Details TBA.
• Checkpoint #5: In this checkpoint you'll document your I/O system and how it works with your processor. VGA, UART, PS/2 keyboard, mouse, audio, analog/digital, etc. are all possibilities. Details TBA.



6. Final Report and Demo: Here is a description of the final report and documentation There are three parts to the final report:
   1. Demo Day! I'd like each team to set up their project in the DSL on Friday, December 12, from 1:00-3:00pm so that we can invite people in to see what you've been up to. As part of the demo your team should prepare a poster that describes the interesting parts of your project.
   2. Final Project Paper: This is a conference-style paper, two-column, in ACM Proceedings format, no more than 8 pages, that describes your project and your demo. See the handout for more details. The paper format can be found here in both Word and LaTeX templates. Due Wednesday, December 17, 5:00pm This should be handed in as hard copy.
   3. Final Project Data: This is a collection of Verilog, schematics, code listings, user guides to your application, user guides for your assembler, and other documentataion about your project. See the handout for more details. Due Wednesday, December 17, 5:00pm This can be handed in as hard copy or on-line. Please include a README file that says what everything is.
   
   
7. Group Evlaution Form This is a form you should use to evaluate you and your group in terms of what everyone did. Every group member should fill out their own copy of the form and turn it in separately. This is a confidential evaluation where you can tell me how well you think the rest of your group did. You can turn it in via email or by hardcopy. Due on Wednesday Dec 12th.
   
   
8. Class evalution form This is a form you can use to give me confidential feedback on how you think the class went this semester. Let me know what you liked and didn't like, what worked, and what could have worked better. You don't need to sign this form! You can turn it in to the SoC office, or slip it under my door when I'm not here.

Slides

• Introduction to CS/EE 3710: as PDF, six slides to a page, and two slides to a page
• Introduction to the CR-16: as PDF, six slides to a page, and two slides to a page
• Verilog Review: as PDF, six slides to a page, and two slides to a page
• Verilog Examples: as PDF, six slides to a page, and two slides to a page
• Mini-MIPS description (see Lab 2): as PDF, six slides to a page, and two slides to a page
• Slides about displays and VGA: as PDF, six slides to a page, and two slides to a page
• Slides about other I/O on the Spartan 3e board: as PDF, six slides to a page, and two slides to a page

Information

• Xilinx Boards: We'll be using the Spartan3-E "starter" board from Xilinx this semester. This is a very powerful board that includes the following:
  • FPGA: Spartan-3E FPGA (XC3S500E-4FG320C)
    • 500,000 gate equivalents, plus 40Kbytes of onboard RAM
  • Clock: 50 MHz crystal clock oscillator
  • Memory:
    • 128 Mbit Parallel Flash
    • 16 Mbit SPI Flash
    • 64 MByte DDR SDRAM
  • Connectors and Interfaces:
    • Ethernet 10/100 Phy
    • JTAG USB download
    • Two 9-pin RS-232 serial port
    • VGA output connector
    • PS/2- style mouse/keyboard port, rotary encoder with push button
    • Four slide switches
    • Eight individual LED outputs
    • Four momentary-contact push buttons
    • 100-Pin expansion connection ports 
    • Three 6-pin expansion connectors
  • Display: 16 character - 2 Line LCD
  • Details of the board can be found here in the Spartan-3E Starter Kit User Guide
  • Here is the Spartan-3E Family Data Sheet for the FPGAs
  • Here is the Spartan-3E Family User Guide for the FPGAs
  • In this directory you can find all sorts of documentation from Xilinx about various aspects of the Spartan-3E
    
• Baseline processor architcture: Our baseline Instruction Set Architecture (ISA) is based on the National Semiconductor CR-16 microcontroller.
  • Here is the CS/EE3710 ISA which is a subset of CR-16 with simplified instruction encoding
  • Here is a link to the actual CR-16 definition from National (note that this is mostly for information, we will be starting from the CS/EE 3710 version above)
    
• Xilinx ISE WebPACK tools: We'll be using the free ISE WebPACK tool from Xlinx for design entry, synthesis, simulation, and mapping the design to the Spartan-3E board. We'll be using the latest version, v10.1.
  • You can download WebPACK from here. You'll have to register with Xilinx, but the tool download is free. Xilinx claims that it runs under both Windows and Linux, but I've only tried the Windows version.
  • Here is a tutorial I've written on how to use the ISE10.1 tools with the Spartan-3E board.
  • If you haven't ever used the tools before, there are other tutorials on the CS/EE 3700 web site
    
  • Here is a Xilinx web site with lots of ISE/Spartan3 documentation.
• Verilog: We'll be using Verilog as a hardware description language this semester. I'm not requiring a Verilog text, but there are lots of good ones out there. Some books that are recommended (and are available at the Marriott Library) are:
  • Verilog Digital System Design - by Zainalabedin Navabi. (Good description of event driven simulation, blocking and non-blocking assignments, and other basic concepts. )
  • Verilog HDL : A guide to digital design and synthesis - Samir Palnitkar. Priyank Kalla, who has taught 3710 a number of times, highly recommends this book
  • Verilog Styles for Synthesis of Digital Systems - David R. Smith, Paul D. Franzon. These Professors have developed high-quality advanced Courses on Verilog Design, CAD & Synthesis.
  • Appendix A in CMOS VLSI Design (3rd ed.) by Neil Weste and David Harris is a nice compact description of Verilog, and how various Verilog constructs map to hardware
    
• There are also lots of places on the web to get Verilog information
• http://www.verilog.net . The name says it all. Click on the DOCS and tutorial links, and you'll find everything that you will need.
• Single-page reference sheet on Verilog syntax in PDF.
• A multi-page Verilog quick reference sheet .
• A longer Verilog Quick Reference guide in PDF
• Yet another Verilog guide . This one is an introduction to Verilog from Daniel C. Hyde at Bucknell University. This guide is targeted at simulation.
• Other Information
• Here is a datasheet for the 32kx8 5v SRAM parts that we have. NOTE: As these are 5v parts and you CANNOT put 5v signals back into the FPGA, you will need to use 300-400ohm series resistors on EVERY signal that will drive data back to the FPGA if you use these chips. See the section in the Spartan3e Starter Kit User Guide on Voltage Compatability on page 42 for an example of interfacing to a 5v part on the Spartan3e board. To use these chips you would wire them on a proto board or wire wrap board that connects to the 100-pin (43 usable I/O pins) connector on the right side of your board. Check with Travis in the DSL if you'd like to check one of these extender boards out along with some SRAM chips.
• Here is a datasheet for a chip that contains 8 separate resistors that you can use for interfacing the SRAM data path with the Spartan FPGA.
• Here is a site with lots of information about PS/2 keyboard and mouse interfaces.
• Here is a site with lots of VGA timing information.