Title:	ECE/CS 6712 - Digital IC Projects Testing, Spring 2009
Instructor:	Ken Stevens, kstevens@ece.utah.edu, MEB 4506, 585-9176
Classes:	TBD
Office Hours:	by appointment
Web Page:	www.eng.utah.edu/~kstevens/6712/6712.html
Prerequisites:	MOSIS fabricated chip from ECE/CS 5710/6710/6770

This course is for students who have designed and fabricated a digital integrated circuit through MOSIS in conjunction with ECE/CS 5710, 6710, or 6770. The options for evaluating functionality, performance, power, and radiation will be discussed along with the equipment usage and options. Students will become familiar with the Tektronix LV500 chip tester and logic analyzers. The characterization of the chip will be carried out, and a report will be presented to the class. The portion of this report suitable for satisfying MOSIS fabrication requirements will be submitted.

Required Textbook:
None. However, course materials and documentation will be provided.

Disability:	If you have one that needs addressing contact the instructor immediately in the beginning of class.
Add/Drop Policy:	The University is very strict on this, and we abide by their policy in this course.
Incomplete Policy:	Due to the project nature of the class, you cannot get an incomplete unless you have a documented medical or legal emergency or military call.

• Include a schmoo plot in your report.
• E-mail me all your test data, including the .msa used to create your functional tests (if done on the lv500), the schmoo plots, your binary schmoo file, and any other testing files you used to test your chip.
• If you had a graphics chip, a photo of the screen output needs to be included in your report.
• If you had errors in your design, report what you feel the problem was, and if you think it was a logic, layout, timing, or other error.
• For MOSIS you must include yield data:
  1. Number of parts received and tested.
  2. Number of parts functional.
  3. Speed of the parts.

The 74F547 Tutorial must be passed off with the instructor before testing your chip.

• The MOSIS fabrication schedule for your chips submitted from 5710/6710.
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• Slides that introduce the LV500 chip tester formatted as color powerpoint or black and white with two, and six slides to a page.
• The DUTmap.txt file describes how your chip pins map to the sector.channel assignments on the class DUT card. You may also want to refer to the DUT map picture that shows the orientation of your socket and the class DUT card.
• An example msa file for the tutorial using the 74F547 chip on the lv512 tester. You can also see the msa file that is produced by translating the lv512 tutorial setup into a .msa file and ftping the file back to a workstation.
• An msa template file for the lv514 tester with our class DUT card.
• A Linux compiled program to convert the binary schmoo files from the tester into an ASCII schmoo plot or a tab delimited file you could import into excel.
• The source files for the schmoo program in tar gzipped format.

These are the project reports from the students 2006:

• Minesweeper by Will Felt, Evan Neal, Vamsi Mudarapu, and Jordan Savage.

• Digital VLSI Slot Machine by Christopher Condrat and Heather Malko.

• Video Poker System on a Chip by Preston Thomson and Travis Johnson.