Spring 2011: CS 7810 and CS 7960-002 Advanced Computer Architecture
General Information:
- Venue: MEB 3105
- Time: Tuesday, Thursday 10:45am - 12:05pm
- Instructor: Rajeev Balasubramonian, email: rajeev, MEB 3414, office hours: by appointment
- Pre-Requisite: CS/EE 6810 or equivalent
- Main Textbook: "Parallel Computer Architecture", Culler, Singh, Gupta.
Reference textbook for memory systems: "Memory Systems: Cache, DRAM, Disk", Jacob, Ng, Wang.
Reference textbook for parallel algorithms: "Introduction to Parallel Algorithms and Architectures: Arrays, Trees, Hypercubes", Leighton.
Reference textbook for interconnection networks: "Principles and Practices of Interconnection Networks", Dally and Towles.
Reference textbook for transactional memory: "Transactional Memory", Larus and Rajwar.
- Class mailing list: cs7810@list.eng.utah.edu. Visit the mailman system to sign up or modify.
Course Description
The course will be based on advanced topics regarding multi-core hardware: cache coherence protocols, cache hierarchies, consistency models, transactional memory, interconnection networks, memory systems, core design, and parallel algorithms.
Students are expected to present a conference paper (for about 20-30 mins) related to their project in one of the classes in March-April. A project presentation is expected in the last week of classes. Final project reports are due early May.
Students that have previously taken either cs7820 or cs7810 are advised to register for cs7960-002 for 1 credit and only attend the new lectures that have been added this year.
College of Engineering Add/Drop Policy:
Guidelines from the college.
Special Needs:
The University of Utah seeks to provide equal access to its programs,
services and activities for people with disabilities. If you will
need accommodations in the class, reasonable prior notice needs to be
given to the Center for Disability Services, 162 Olpin Union Building,
581-5020 (V/TDD). CDS will work with you and the instructor to make
arrangements for accommodations.
All written information in this course can be made available in
alternative format with prior notification to the Center for
Disability Services.
Grading:
The course project accounts for 70% of the class grade.
10% will be based on your paper presentation.
The remaining 20% will be based on a take-home final.
Class Schedule
Slides will be posted a few hours before class.
- Tu 11th Jan:
Introduction and Snooping Protocols (Chapter 1, 2)
Slides:
(powerpoint)
(pdf)
- Th 13th Jan:
Snooping and Directory Protocols (Chapters 5, 6, 8)
Slides:
(powerpoint)
(pdf)
- Tu 18th Jan:
Directory-based Implementations (Chapter 8)
Slides:
(powerpoint)
(pdf)
Slides on Synchronization (not covered in class):
(powerpoint)
(pdf)
Slides on Hardware/Software trade-offs (Chapter 9) (not covered in class)
(powerpoint)
(pdf)
- Th 20th Jan:
Directory protocols and Transactional Memory Intro (Larus and Rajwar book)
Slides:
(powerpoint)
(pdf)
- Tu 25th Jan:
Transactional Memory -- TCC and LogTM intro
Slides:
(powerpoint)
(pdf)
- Th 27th Jan:
Transactional Memory -- LogTM and Pathologies
Slides:
(powerpoint)
(pdf)
- Tu 1st Feb:
Shared memory consistency models tutorial (Adve and Gharachorloo)
Slides:
(powerpoint)
(pdf)
- Th 3rd Feb:
Large cache hierarchy design: shared/private/NUCA
Slides:
(powerpoint)
(pdf)
- Tu 8th Feb:
Large Caches: partitioning and replacement
Slides:
(powerpoint)
(pdf)
- Th 10th Feb:
Large Caches: replacement, associativity, prefetch
Slides:
(powerpoint)
(pdf)
- Tu 15th Feb:
Large Caches: prefetch, cache network
Slides:
(powerpoint)
(pdf)
- Th 17th Feb:
Memory Systems: intro
Slides:
(powerpoint)
(pdf)
- Tu 22nd Feb:
Memory Systems: energy innovations, row buffer management, scheduling
Slides:
(powerpoint)
(pdf)
- Th 24th Feb:
Memory Systems: reliability, PCM
Slides:
(powerpoint)
(pdf)
- Tu 1st Mar:
PCM wrap-up
Slides:
(powerpoint)
(pdf)
- Th 3rd Mar:
Interconnection network basics
Slides:
(powerpoint)
(pdf)
- Tu 8th Mar: No Class
- Th 10th Mar:
Interconnection network innovations
Slides:
(powerpoint)
(pdf)
- Tu 15th Mar:
Core Design Basics
Slides:
(powerpoint)
(pdf)
- Th 17th Mar:
Core Design Innovations
Slides:
(powerpoint)
(pdf)
- Tu 22nd Mar: Spring break
- Th 24th Mar: Spring break
- Tu 29th Mar:
Core Design Innovations
Slides:
(powerpoint)
(pdf)
- Th 31st Mar: Parallel algorithms
Parallel algorithms (Leighton book)
Slides:
(powerpoint)
(pdf)
Student Paper Discussions:
- Tu 5th Apr:
Hardware/Software Solutions for DRAM Thermal Management
Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory
Evaluating Bufferless Flow Control for On-Chip Networks
Micro-Pages: Increasing DRAM Efficiency with Locality-Aware Data Placement
- Th 7th Apr:
Prediction in Dynamic SDRAM Controller Policies
Dynamic Branch Prediction with Perceptrons
A Case for Bufferless Routing in On-Chip Networks
- Tu 12th Apr: Guest lecture, Ani Udipi, Silicon Photonic interfaces
- Th 14th Apr:
Express Cube Topologies for On-Chip Interconnects
Future Scaling of Processor-Memory Interfaces
A Case for MLP-Aware Cache Replacement
- Tu 19th Apr:
CHIPPER: A Low-Complexity Bufferless Deflection Router
Scavenger: A New Last Level Cache Architecture with Global Block Priority
- Th 21st Apr:
Student project presentations.
- Tu 26th Apr:
Student project presentations.