vVideo Schematic Module

Specification

Inputs

· clk – 10 megahertz, 50% duty-cycle clock.

· nRst – asynchronous reset when low.

· vCntEna –valid for one clock cycle (100 nsec) indicating that the vertical counter should change.

Outputs

• vSync – rising edge on this pulse indicates that a frame (entire picture) is complete and that another one is to begin. This signal is sent to the monitor to control its vertical timing.
• vBright – valid during that portion of each line time when video (picture) is to be sent to the monitor.
• Vcnt[9:0] – 10 bit vertical counter. The low order 8 bits of the counter range from 0 to 255 when vBright is asserted.

Suggested implementation

vVideo should be based on 10 bit counter that changes value only when vCntEna is asserted (with the obvious exception of clearing when the asynchronous reset signal, nRst, is low). This counter will be used to create the timing cycle depicted in this waveform. Notice the relationship between vSync and hBright. A closer view of the beginning of the cycle is given in this waveform notice that the 10 bit counter, Vcnt[9:0], at 000 and counts up to 10’h22B which is 555. Notice that the count changes only in the cycle after vCntEna is asserted. Since vCntEna is asserted every 30 microseconds, the period of each frame is 16.68 milliseconds (30 microseconds/line * 556 lines). vBright starts when Vcnt is 0 and ends when it is 10’h0ff as shown in this waveform. vSync is asserted for three line times between Vcnt[9:0] == 10’h187 and Vcnt[9:0]==10’h189 as shown here

An asynchronous reset cycle is shown here.

The test bench for vVideo can be similar to the one created for hVideo with the addition of an always block for vCntEna.