Mini_Project Top Module

Specification

Inputs

· CLK – 10 megahertz, 50% duty-cycle clock.

· nRst – asynchronous reset when high.

Outputs

• hSync – rising edge on this pulse indicates that a horizontal line is complete and that another one is to begin. This signal is used by the verilog test bench.
• nhSync – inverted hSync. This is the polarity required by the monitor to control its horizontal timing.
• hBright – valid during that portion of each line time when video (picture) is to be sent to the monitor
• vSync – rising edge on this pulse indicates that a frame (entire picture) is complete and that another one is to begin. This signal is used by the verilog test bench.
• nvSync –inverted vSync. This is the polarity required by the monitor to control its vertical timing.
• vBright – valid during that portion of each line time when video (picture) is to be sent to the monitor.
• VidOut – video output signal. This signal is asserted in the bright parts of the image and not asserted where the image is dark.

Test Bench

Everyone will use the same test bench to test the top module. The test bench is located at :

http://www.eng.utah.edu/~cs6710/MiniProject/

download the file TopBench.v from this directory. Also notice that this directory contains a file named booah.txt which is the output that a properly functioning Top Module will produce when TopBench.v is used as a test bench.