hVideo Verilog Module
Specification
Inputs
- clk
– 10 megahertz, 50% duty-cycle clock.
- rst – asynchronous reset when high.
Outputs
- hSync
– 2 microsecond positive pulse.
Repeats every 30 microseconds.
- vCntEna
– 100 nanosecond positive pulse. Rises 500 nanoseconds after the rising edge of hSync.
- hBright – 12.8
microsecond positive pulse. Rises
12.7 microseconds after the rising edge of hSync.
- HA[6:0] – This number is valid during the
interval when hBright is set. It starts at 7’h0 during the first clock
interval of hBright valid. It counts up to 7’h7F, coincident with the
last clock interval when hBright is valid.
Notes
- hSync
– Rising edge on this pulse indicates that a horizontal line is complete
and that another one is to begin.
This signal will be sent to the monitor to control its horizontal
timing.
- vCntEna
– This pulse indicates that the vertical counter should change.
- hBright – This
pulse is valid during that portion
of each line time when video (picture) is to be sent to the monitor
- HA[6:0] – seven bit counter used to select
picture elements to be sent to the monitor. This number starts at zero during the
first clock interval of hBright valid. It counts up to 127 which is the last
clock interval when hBright is valid.
Suggested implementation
hVideo should be based on
free-running 9 bit counter. This counter
will be used to create the timing cycle depicted in this waveform. Notice the relationships between hSync, hBright, HA[6:0] and vCntEna. A closer view of the beginning of the cycle
is given in this waveform
notice that the 9 bit counter is called hcnt[8:0] and that HA[6:0] is the unmodified lowest 7 of the 9
bits. The counter starts at 000 and
counts up to 9’h12B which is 299. The
cycle time of the counter is 30.0 microseconds (300 cycles @
100 nsec/cycle). vCntEna is sent to the Vertical Module when hcnt is 6. The
Vertical Module will only change state when vCntEna
is asserted. hSync starts when hcnt is 1
and stops when hcnt is 9’h014 as seen in this waveform.
hBright starts when hcnt is
9’h080 here
and stops when hcnt is 9’h0FF as shown in this waveform.
An asynchronous reset cycle is shown here.
Here is a simple test bench for hVideo.v
can be found in the file hTestBench.v at
http://www.eng.utah.edu/~cs6710/MiniProject/