CS/EE 5710/6710 Syllabus
Digital VLSI Design
Fall 2011

• Office Hours: Tuesday and Thursday after class, when my office door is open, or by appointment

• Consultation hours (in the CADE lab): Mon & Wed 1:00-2:00pm, Tue & Thu 1:00-2:30pm
  
  

This is a class in VLSI design not in digital system design, I'll assume that you know how to design and implement combinational and sequential circuits digital (i.e. finite state machines, data path circuits, and using FSM's to control datapaths). The project will be based on building a digital standard cell library and then using it to build a digital system so knowing some computer architecture will definitely help. You should be comfortable with computer CAD tools for hardware design. We'll be using tools from Cadence and Synopsys. You don't need to know these tools specifically, but I'll assume that you've used CAD tools of some sort.

We'll also use Digital VLSI Chip Design with Cadence and Synopsys CAD Tools by Erik Brunvand as a lab manual. Published by Addison-Wesley, c2010, ISBN 978-0321547996. This book is available at a special price in a bundle with the CMOS VLSI Design textbook. That bundled version should be what is available in our University of Utah bookstore.

I'll put the first few chapters on-line for this class. These are draft chapters, but they're very similar to the published chapters. Please respect these files and don't copy them or let them escape out to the web. The chapters will be available only from the utah.edu web domain.

You are, of course, also free to read the CAD tool documentation and learn more right from the source. However, I encourage you to start with the Lab Manual because I know that using the tools in this way works. If you discover some new trick about using the tools, I'd love to hear about it!

The following draft book chapters are in PDF format: Title page, Contents, and Preface Chapter1: Getting Started Chapter2: Cadence Design Framewwork Chapter3: Composer Schematic Capture Chapter4: Verilog Simulation

• cs6710@list.eng.utah.edu will go to all students in the class. If you haven't been getting email sent to this list, you need to add yourself to the list. You can do this at https://sympa.eng.utah.edu/sympa/info/cs6710
• teach-cs6710@list.eng.utah.edu - this list will go to both Erik and the TAand is the best way to ask questions about things going on in the class.

Important Information

q College guidelines for adding, dropping, and other administrative issues can be found here.

q Cheating will not be tolerated! A discussion of this issue can be found here

q The University of Utah provides reasonable accommodation to the known disabilities of employees and students. If you need special accommodations, please let the instructor know at the beginning of the semester.

Course Description

This is an introductory course in VLSI where you will go from the low level physical transistor and mask design of your own cell library, all the way to the design, implementation, and fabrication of a significant digital integrated circuit.

Many aspects of Digital VLSI design will be introduced in order to take this significant and enjoyable design journey. However, note that this is not a course in digital system design or computer architecture. You will already need to know boolean logic and how to design and implement combinational and sequential digital circuits (such as adders and other datapath logic, and finite state machines). The project will also require some knowledge of computer architecture for you to complete a moderately large digital design.

Topics that will be covered in lectures include:

• Basic transistor theory
• CMOS processing
• Mask layout and design rules
• VLSI CAD tools
• Circuit simulation and characterization
• Custom datapath circuit design
• Standard cell design and use
• Library-based circuit synthesis
• Full chip assembly

The class will require extensive use of CAD tools. All of the CAD tools required will be available in the CADE lab. Students must have an account that will allow them to use the CADE machines. These tools do not run on Windows. Therefore some familiarity with Linux and the X window system is required for this course.

The tools will be discussed in class and you will receive the aid of the TA in the labs and project. However, there is no specific lab class that you are required to attend. You can perform the labs and your project at your own convenience, either in the CADE lab at the University, or across the network. Remember that nothing can replace taking the time to read the CAD tool documentation.

Integrated circuit design is mastered only through experience, so this is a hands-on course with lots of labs and project time required. The homework, as well as lectures, will be closely tied to the term project, the design of a simple standard cell library and then the use of that library to design a project. The initial design of cells for the project will be done individually. You must complete the design of these cells on time. You are encouraged to interact with others, but until you are asked to form teams, the work on your cell designs, simulations, etc., must be your own.

The final library and project will be done in teams of 3-4 students. The project must be completed, and you must submit a final report in the format specified.

Fabrication of your final project is possible thanks to funding provided through the MOSIS service. Little is more rewarding that creating a functional integrated circuit. Little is more disappointing than spending time on a design only to have in be non-functional. Therefore, careful design practices must be followed if you are to fabricate your chip including sufficient Design-For-Test, validation of your design, and a quality design review. If you do fabricate the chip, you will be required to take ECE/CS 6712 in Spring 2012 (1cr) to test and report on the results. 6712 is a fun class and a reward to those who make the effort to fabricate their designs.

This semester I would like to add an additional subject to the course: general design principles. I feel that there are principles of good design that transcend "engineering design" or "fine arts design" or "industrial design" or "design aesthetics." At some level we can all be aware of good design vs. bad design, even for end results that meet all the specs. VLSI design has many aspects of engineering design, but almost as many of graphic design. CMOS layout is a spatial puzzle where good drawing, 2d, and 3d visualiztion skills are invaluable. Chip layout is another area that has direct ties with visual design and 2d/3d planning.

This semester all students will be required to keep a sketchbook. I'll give out sketchbook assignments along with lab assignments. The sketchbook assignments will be designed to help you explore and develop 2d/3d visualization and design skills. You will not be graded on the quality of your sketches! You will be graded on whether you participate in the sketchbook assignments.

Sketchbook Gallery: There is a long history of artists and designers keeping sketchbooks as part of their practice, and their daily lives. I'll post links to example sketchbooks from a variety of sources here. Use them as inspiration, not as exact examples to emulate.

About the CAD tools

We'll be using CAD tools from Cadence and Synopsys this semester. These are "industrial strength" CAD tools and are the same tools that major chip makers use to build commercial chips. As such they are very powerful tools but they aren't necessarily intuitive to use. They are very efficient tools for the power user, but they sometimes have a steep learning curve.

The University of Utah is part of the Cadence University Program. Our Cadence program web page is here.

Our lab manual is based on many years of using these tools and teaching classes based on these tools. The book describes in detail how to use each of the tools that we'll use in this course, and includes tutorials that demonstrate how the tools are used at each step in the design of a digital integrated circuit.

Note that the CAD book is based on the Cadence V5 software, but we have upgraded the Cadence software to V6. This is a huge change to the underlying design database that the Cadence software uses, but involves only fairly minor changes to the user interface. I am writing a V5 to V6 conversion guide that should update the CAD manual for the V6 software. It's available here in PDF. I'll be updating and expanding on it as the semester progresses. If you find an issue that I haven't covered, or mistakes, please let me know! Thanks. NEW (11/16/11): I've updated the V6 guide for the entire book, and added material about hierarchical place and route flows.

If you want to run the CAD tools remotely, there are a wide variety of options. You can use an X server and login to the CADE machines using ssh -Y to tell that connection to forward the window connections to your local X server. Or you can use something like vnc to set up a remote window connetion and run the tools on the CADE machine but have the virtual window of that machine show up on your local machine. I find that vnc works better than the X forwarding approach, but your milage may vary.

Here is a document that describes one way to get vnc up and running. It's a few years old, but should still apply. Basically you need to have a vnc client running on your remote machine, and then login to a CADE machine and fire up a vnc server on that machine. Once that's going, your local client can connect to the CADE server.

Assignments and Labs

The labs for this class are on a very tight schedule in order to complete the project by the end of the semester. Any slip in the schedule will cause lots of headaches later on! Students will need to be aware of the schedule and complete labs on time. There is generally no provision for late work.

The lab contents will be available here as soon as we have them ready...

At some point we're going to start electronic handin of much of the assignment (stay tuned for details). General instructions for the CADE handin process are located here. Instructions for each specific assignment will be either in the assignment or emailed to the class mailing list.

q Review assignment. In PDF. This assignment will be graded! It will just be graded pass/fail though. If you can answer all the questions easily then you probably have the right background for this course. If you can't, you will need to brush up on some of your digital logic background! Please take this seriously! If you have trouble with this exam, you will also have trouble with the project! Due Tuesday, August 30th in class.

q CAD1: in PDF - Cadence schematic capture and Verilog simulation. Reading: CAD Manual Chapters 1-4. Due Friday September 2nd. The sketchbook portion of this assignment is due Wednesday, August 31st at 5:00pm.

q CAD2: in PDF - Virtuoso layout, DRC, LVS, Analog simulation. Reading CAD manual Chapters 5-7. Due Monday September 12^th.

q CAD3: in PDF - FF/Register design. Reading: Lab Manual Chapters 3-7, Book Chapter 1 (section 1.4). Also peek ahead at Chapter 10. Due Thursday September 22nd. Note that there is a printed part to hand in, and a tar file to hand in electronically with handin.

q CAD4: in PDF - DC simulation, transistor operation. Reading: CAD manual Chapter 7, Book Chapter 2. Due Thursday September 29^th. For CAD4, please print out the various circuits and output waveforms and turn in on paper, or convert everything to PDF and use handin. We won't need the Cadence libraries, just the printouts (schematics, waveforms, book problems, etc.)

q CAD5: in PDF - Initial 5-cell Library. Group Assignment! Reading: CAD manual Chapters 6, 8. Due Tuesday October 18^th.
For CAD5 use electronic handin for your cell library project directory (Lib6710_xx) and data directory (LibData_xx) as described in the lab handout

Send email to teach-cs6710@eng.utah.edu telling us who is in your group, their CADE ID's, and their emails, by Friday October 7th

q CAD6: in PDF - Seven more cells to make a 12-cell Library. Group Assignment! Reading: CAD manual Chapters 8-10, and the paper Compact yet High-Performance (CyHP) Library for Short Time-to-Market with New Technologies by Nguyen Minh Duc and Takayasu Sakurai. This paper makes a case that a small (11 or 20 cells) library can perform almost as well as a 400 cell library when used with Synopsys design compiler and standard benchmarks. Due Tuesday, October 25th. Now due Thursday, Oct 27th, 11:59pm

For CAD6 use electronic handin for your cell library project directory (Lib6710_xx), and data directory (LibData_xx) as described in the handout.

q CAD7: in PDF - A few more cells, and place and route of a controller example. Reading: CAD manual Chapter 11. Due Tuesday, November 1st. Now due Thursday November 3rd, 11:59pm

q CAD8: in PDF- Project Proposal... Tell me some details about your planned project. Due Thursday Nov 17th, 5:15pm.

q Final Report - Final reports are due on Monday Dec, 19. Details were sent out to the class email list. Handin to the "report" assignment, or print PDF and put in the box by SoC office.

- Along with your final project reports, there are two evaluations that *each* team member should fill out

1. This is an evaluation of your temmates. Every team member should fill one out. These go to me, and not to anyone else. The evaluations let me know how you think the other members of your team contributed to the project. Your should sign your name on this one so I can tell who did the evaluating. I won't let anyone know what you said.
2. This is an evaluation of the class - tell me what you thought of the class, what you liked, and what could be done better. You should *not* sign your name on this one so that you can feel free to give me honest feedback.

 

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Class Schedule

Week	Class Schedule - Fall 2011	Lecture Slides	Reading
8/23-25	Intro and transistor switch-level circuits	Intro slides: 6 to a page and 2 to a page in PDF Switch-level circuits: 6 to a page and 2 to a page in PDF David Harris' slides: 6 to a page and 2 to a page in PDF	Chapter 1, sections 1.1-1.4
8/30 - 9/1	more transistor switch level circuits, intro to layout, design rules, and simple Verilog for testbenches	Layout 1: 6 to a page and 2 to a page in PDF Testbenches: 6 to a page and 2 to a page in PDF Chip Pics: 6 to a page and 2 to a page in PDF	Section 1.4 Looking forward to Chapters 9 and 10
9/6-8	more layout, line of diffusion, Euler paths	Layout 2: 6 to a page and 2 to a page in PDF	Sections 1.5.2-1.5.5, and 3.3
9/13-15	MOS transistor theory and behavior	Transistors: 6 to a page and 2 to a page in PDF Tessellations: 6 to a page and 2 to a page in PDF - other tesselation resources: Tessellations_by_Recognizable_Figures Tessellation.pdf library.thinkquest.org/16661/ tessellations.org/ www.mcescher.com/	Chapter 2,and some of Chapters 5 and 6 on power and interconnect modeling
9/20-22	CMOS processing and fabrication	Fab: 6 to a page and 2 to a page in PDF	Section 1.5, and Chapter 3
9/27-29	Logical effort transistor sizing and analysis	LE: 6 to a page and 2 to a page in PDF David Harris' slides: 6 to a page and 2 to a page in PDF	Chapter 4, especially Sections 4.4 and 4.5
10/4-6	Verilog for synthesis, synthesis overview, review of CAD3 register layouts
10/11-13	No Class - Fall Break
10/18-20	Verilog for synthesis, Synopsys overview (synthesis)	Synthesis: 6 to a page and 2 to a page in PDF	Appendix A
10/25-27	SOC Encounter overview (place and route)	P&R: 6 to a page and 2 to a page in PDF Inverter footprints: 6 to a page and 2 to a page	Chapter 11
11/1-3	NO LECTURES ON TUESDAY- Sign up for scheduled group project proposal meetings during class time on Tuesday. Lecture as normal on Thursday	Group meetings on 11/1, Shay will lecture on asynchronous digital circuits on 11/3 (Erik is out of town on 11/3)
11/8-10	NO LECTURES ON TUESDAY - sign up for group meetings during class time MIDTERM EXAM on 11/10 Here is a sample midterm to try out...	Group meetings on 11/8 Midterm on 11/10
11/15-17	MIPS example of a complete (small) system, and VGA circuits	MIPS: 6 to a page and 2 to a page in PDF VGA: 6 to a page and 2 to a page in PDF	Chapter 12
11/22	Chip assembly using CCAR on 11/22 (Thanksgiving on 11/24)	Chip assembly: 6 to a page and 2 to a page in PDF Pads and pad rings: 6 to a page, 2 to a page in PDF	Notes linked to the class web ste
11/29 - 12/1	NO LECTURES - Sign up for scheduled group design reviews during class time this week	Group Meetings on both Tuesday and Thursday
12/6-8	Testing preview? (CS/ECE 6712), student project presentations in class?	Testing: 6 to a page and 2 to a page in PDF MemcellsF09: 6 to a page and 2 to a page in PDF	Chapter 15
Wed 12/14 (finals week)	Final project due

 

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Grading Policy

Grading will be based on participation. Expected participation includes:

o   Homework: Written homework will take the form of problem sets, project proposals, and other written work.

o   Labs: Labs involve mask-layout design of cells that will be used in your semester project. We will use CAD tools from Cadence and Synopsys runing on linux in the CADE lab.

o   Design Review: A short presentation on your project given to the class.

o   Mid-term Exam: There will be one exam given sometime in the middle of the semester.

o   Class Project: The class project will require the design of a small digital standard cell library that will then be used as a target library for a moderate sized chip design. Class members will join design teams for the implementation of the design. More details on the format of the final report will be available later in the semester.

o   Graduate Students: Those taking the graduate level course will have additional requirements that include a more rigorous project or design flow and the review of two papers relating to VLSI from journals or conferences in the area. These could be related to the project being implemented.

Percentages for grades are as follows:

§    Labs (cell designs) & Homework: 40%

§    Design Review: 5%

§    Mid-term Exam: 15%

§    Project (design and report) 40%

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Helpful Information

q Here's a link to a page with lots of VGA timing info. Note that this is "official timing" information, and most VGA displays are quite forgiving if you are consistent with your own timing.

q This page from the XESS company has some examples of VGA controllers targetted at their Xilinx-based boards. So, memory details would have to be finessed for custom chips, but the basics might be interesting. The appnote for the simple controller for the ancient XS-40 board is a good basic design, although it's in VHDL in the appnote...

q Here's a link to a site with information about interfacing to a PS/2 keyboard and mouse. It describes the timing interface and the communication protocol that keyboards and mice use to send data through that link. Note that PS/2 keyboards, for example, don't send ascii. They send "make codes" and "break codes" on key press and key release that encode which physical key has been pressed. You need to map those keys to the letters using those codes if you want ascii.

q Chapter one from Sutherland, Sproull, and Harris' book on Logic Effort is here in PDF. The website for the book is located here

q A document by Eric Marsman from University of Michigan that describes a layout and floorplanning approach in a three metal process. This is a nice basic guide to planning interconnect issues. It's in PDF.

q A guide to basic electronics including MOS transistors: Appendix B from Contemporary Logic Design by Randy Katz. You don't need to know the sections on bipolar or diode logic. The MOS section is the most important.

q The SCN3M_SUBM SCMOS design rules from MOSIS, translated to microns, in PDF format, and in Word format.

q The official SCMOS Rev8 design rules at MOSIS

q A link to Reid Harrison's CS/EE 5720/6720 Analog VLSI class. They are also using the NCSU CDK and the SCMOS rules so you can find more information here including tutorials on analog simulation of designs built with the NCSU CDK, and a layout tutorial.

q Information on Chip Fabrication: MOSIS (MOS Implementation Service) home page

q LaTeX style files for producing IEEE-formatted two-column papers: A .cls style file with formatting information, a .bst bibliography style file, and a sample .tex file that demonstrates how it all should be used.

q A Microsoft Word example file that shows how to get an IEEE format in MS Word.

q A data sheet on the HM6264 8kX8 SRAM from the DSL lab kits. This is a good example of a generic SRAM that shows read and write protocols.

q Documentation from Tanner Research about their digital pads in PDF. We'll be using these pads for our chip designs.

q A page from Americn Microsemiconductor that has lots of tutorials on various semiconductor topics.

q Here's a paper that I wrote a few years ago that describes a simple stack based architecture similar to the transputer that might make a great project. Even if you don't use this exact architecture, stack-based machine make nice simple processor architectures for those wanting to do a processor project. You definitely don't have to do this as a self-timed processor! It's a perfectly good synchronous stack machine too.

q Here are a couple papers from the Journal of Solid State Circuits about latches and flip flops. These are just a couple examples, there are lots of papers about this! These papers analyze different latch and flip flop circuits for speed and power performance.

    o Comparative Analysis of Master Slave Latches and Flip-Flops for High-Performance and Low-Power Systems by Vladimir Stojanovic and Vojin G. Oklobdzija

    o New single-Clock CMOS LAtches and Flipflops with Improved Speed and Power Savings by Jiren Yuan and Christer Svensson

q Compact yet High-Performance (CyHP) Library for Short Time-to-Market with New Technologies by Nguyen Minh Duc and Takayasu Sakurai. This paper makes a case that a small (11 or 20 cells) library can perform almost as well as a 400 cell library when used with Synopsys design compiler and standard benchmarks.

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Tool Information (Cadence, Synopsys, Verilog, etc. )

q Single-page reference sheet on Verilog syntax. This is the language used by the Verilog-XL simulator in Cadence. PDF format

q A Verilog Quick Reference guide (in Postscript)

q Another Verilog guide, this one is a lab from another class, but it talks about simulating Verilog code using the Verilog-XL simulator.

q Yet another Verilog guide. This one is an introduction to Verilog from Daniel C. Hyde at Bucknell University. This guide is targetted at simulation.

q A set of documents from Synopsys that describe good Verilog coding style for synthesis. They are all in linked PDF. Open the Table of Contents and you should be able click on the chapters in that file to open up the chapters.
Note that these files are only accessable to CS/EE 5710/6710 students

     o Table of contents

     o Chapter 1

     o Chapter 2

     o Chapter 3

     o Chapter 4

     o Chapter 5

q A reference manual from Synopsys describing the Verilog synthesis engine.
Note that these files are only accessable to CS/EE 5710/6710 students

     o Table of contents

     o Chapter 1

     o Chapter 2

     o Chapter 3

     o Chapter 4

     o Chapter 5

     o Chapter 6

     o Chapter 7

     o Chapter 8

     o Chapter 9

     o Chapter 10

     o Appendix A

     o Appendix B

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Reference Material

q David Hodges, Analysis and Design of Digital Integrated Circuits (3rd ed), McGraw Hill, 2004.

q Wayne Wolf, Modern VLSI Design (3rd ed), Prentice Hall, 2002.

q Jan M. Rabaey, Digital Integrated Circuits (2nd ed), Prentice Hall, 2003.

q Glasser and Doberpuhl, The Design and Analysis of VLSI Circuits, (most detailed circuit treatment), Addison-Wesley, 1985.

q Michael J. S. Smith, Application-Specific Integrated Circuits, (new, comprehensive, advanced level) Addison-Wesley, 1997.

q Hodges and Jackson, Analysis and Design of Digital Integrated Circuits (Second Edition), McGraw-Hill, 1988.

q Hennessy and Patterson, Computer Organization & Design - The Hardware/Software Interface, (3810 text) Morgan Kaufmann, 1994.

q IEEE Journal of Solid-State Circuits

q EEE Trans. on Computer-Aided Design of Integrated Circuits and Systems

q IEEE International Solid-State Circuits Conference, 1954 -

q Advanced Research in VLSI, 1980-

q IEEE Custom Integrated Circuits Conference, 1979 -

q EE Times, Electronics, Computer Design, EDN...

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