CS/EE 5710/6710 Syllabus
Digital VLSI Design
Fall 2009
General Information
- Instructor: Prof. Erik Brunvand
, 581-4345. Office is MEB 3142. Please use the teach-cs6710@cs mailing list to send email about the class.
- Office Hours: Tuesday and Thursday after class, when my office door is open, or by appointment
- TA: Toren Monson
- Consultation hours (in the CADE lab): Tuesday 11:00-12:15, Thursday 10:30-12:15, 2:00-3:00, Friday 10:30-12:00
- Class: T-Th, 12:25-1:45, WEB 1250
- Prerequisites: CS/EE3700 (Digital Design) or equivalent is required.
CS3810 (Computer Architecture) equivalent is extremely helpful.
This is a class in VLSI design not in digital system design, I'll assume that you know how to design and implement combinational and sequential circuits digital (i.e. finite state machines, data path circuits, and using FSM's to control datapaths). The project will be based on building a digital standard cell library and then using it to build a digital system so knowing some computer architecture will definitely help. You should be comfortable with computer CAD tools for hardware design. We'll be using tools from Cadence and Synopsys. You don't need to know these tools specifically, but I'll assume that you've used CAD tools of some sort.
- Textbook: Principles
of CMOS VLSI Design: A Systems Perspective (3rd Edition), By Neil
Weste, David Harris, Published by Addison-Wesley, c2005, ISBN
0-321-14901-7. Note that there are some Errata (mistakes) that are
listed here.
We'll also use Digital VLSI Chip Design with Cadence and Synopsys CAD Tools by Erik Brunvand as a lab manual. Published by Addison-Wesley, c2010, ISBN 978-0321547996. This book is available at a special price in a bundle with the CMOS VLSI Design textbook. That bundled version should be what is available in our University of Utah bookstore.
- There are two email lists that will be used for this class
- cs6710@list.eng.utah.edu will go to all students in the class. If you haven't been getting email sent to this list, you need to add yourself to the list. You can do this at https://sympa.eng.utah.edu/sympa/info/cs6710
- teach-cs6710@list.eng.utah.edu - this list will go to both Erik and Toren and is the best way to ask questions about things going on in the class.
Important Information
q College guidelines for adding, dropping, and other administrative issues can be found here.
q Cheating will not be tolerated! A discussion of this issue can be found here
q The
Course Description
This is an introductory course in VLSI where you will go from the low level physical transistor and mask design of your own cell library, all the way to the design, implementation, and fabrication of a significant digital integrated circuit.
Many aspects of Digital VLSI design will be introduced in order to take this significant and enjoyable design journey. However, note that this is not a course in digital system design or computer architecture. You will already need to know boolean logic and how to design and implement combinational and sequential digital circuits (such as adders and other datapath logic, and finite state machines). The project will also require some knowledge of computer architecture for you to complete a moderately large digital design.
Topics that will be covered in lectures include:
- Basic transistor theory
- CMOS processing
- Mask layout and design rules
- VLSI CAD tools
- Circuit simulation and characterization
- Custom datapath circuit design
- Standard cell design and use
- Library-based circuit synthesis
- Full chip assembly
The class will require extensive use of CAD tools. All of the CAD tools required will be available in the CADE lab. Students must have an account that will allow them to use the CADE machines. These tools do not run on Windows. Therefore some familiarity with Linux and the X window system is required for this course.
The tools will be discussed in class and you will receive the aid of the TA in the labs and project. However, there is no specific lab class that you are required to attend. You can perform the labs and your project at your own convenience, either in the CADE lab at the University, or across the network. Remember that nothing can replace taking the time to read the CAD tool documentation.
Integrated circuit design is mastered only through experience, so this is a hands-on course with lots of labs and project time required. The homework, as well as lectures, will be closely tied to the term project, the design of a simple standard cell library and then the use of that library to design a project. The initial design of cells for the project will be done individually. You must complete the design of these cells on time. You are encouraged to interact with others, but until you are asked to form teams, the work on your cell designs, simulations, etc., must be your own.
The final library and project will be done in teams of 3-4 students. The project must be completed, and you must submit a final report in the format specified.
Fabrication of your final project is possible thanks to funding provided through the MOSIS service. Little is more rewarding that creating a functional integrated circuit. Little is more disappointing than spending time on a design only to have in be non-functional. Therefore, careful design practices must be followed if you are to fabricate your chip including sufficient Design-For-Test, validation of your design, and a quality design review. If you do fabricate the chip, you will be required to take ECE/CS 6712 in Spring 2010 (1cr) to test and report on the results. 6712 is a fun class and a reward to those who make the effort to fabricate their designs.
About the CAD tools
We'll be using CAD tools from Cadence and Synopsys this semester. These are "industrial strength" CAD tools and are the same tools that major chip makers use to build commercial chips. As such they are very powerful tools but they aren't necessarily intuitive to use. They are very efficient tools for the power user, but they sometimes have a steep learning curve.
Our lab manual is based on many years of using these tools and teaching classes based on these tools. The book describes in detail how to use each of the tools that we'll use in this course, and includes tutorials that demonstrate how the tools are used at each step in the design of a digital integrated circuit.
Assignments and Labs
The labs for this class are on a very tight schedule in order to complete the project by the end of the semester. Any slip in the schedule will cause lots of headaches later on! Students will need to be aware of the schedule and complete labs on time. There is generally no provision for late work.
The lab contents will be available here as soon as we have them ready...
At some point we're going to start electronic handin of much of the assignment (stay tuned for details). General instructions for the CADE handin process are located here. Instructions for each specific assignment will be either in the assignment or emailed to the class mailing list.
q Review assignment. In PDF. This assignment will be graded! It will just be graded pass/fail though. If you can answer all the questions easily then you probably have the right background for this course. If you can't, you will need to brush up on some of your digital logic background! Please take this seriously! If you have trouble with this exam, you will also have trouble with the project! Due Tuesday, September 1st .
q CAD1: in PDF - Cadence schematic capture and Verilog simulation. Reading: CAD Manual Chapters 1-4. Due Friday September 4th .
q CAD2: in PDF - Virtuoso layout, DRC, LVS, Analog simulation. Reading CAD manual Chapters 5-7. Due Monday September 14th.
q CAD3: in PDF - FF/Register design. Reading: Lab Manual Chapters 3-7, Book Chapter 1 (section 1.4). Also peek ahead at Chapter 7. Due Monday September 21st. Note that there is a printed part to hand in, and a tar file to hand in electronically with handin.
q CAD4: in PDF - DC simulation, transistor operation. Reading: CAD manual Chapter 7, Book Chapter 2. Due Monday September 28th. For CAD4, please print out the various circuits and output waveforms and turn in on paper, or convert everything to PDF and use handin. We won't need the Cadence libraries, just the printouts (schematics, waveforms, book problems, etc.)
q CAD5: in PDF - Initial 5-cell Library. Group Assignment! Reading: CAD manual Chapters 6, 8. Due Friday October 9th.
For CAD5 use electronic handin for your cell library project directory (Lib6710_xx) and data directory (LibData_xx) as described in the lab handout.q CAD6: in PDF - Seven more cells to make a 12-cell Library. Group Assignment! Reading: CAD manual Chapters 8-10, and the paper Compact yet High-Performance (CyHP) Library for Short Time-to-Market with New Technologies by Nguyen Minh Duc and Takayasu Sakurai. This paper makes a case that a small (11 or 20 cells) library can perform almost as well as a 400 cell library when used with Synopsys design compiler and standard benchmarks. Due Friday October 23rd.
For CAD6 use electronic handin for your cell library project directory (Lib6710_xx), and data directory (LibData_xx) as described in the handout.q CAD7: in PDF - A few more cells, and place and route of a controller example. Reading: CAD manual Chapter 11. Due date extended! Now due Monday, Nov 2nd at midnight. Handin instructions are in the assignment.
Lecture Slides
I'll put the slides up here as they become available.
q Slides for lecture 1: intro, CMOS transistors as switches. Available in PDF six to a page and in PDF two to a page, Reading: Chapter 1, sections 1.1-1.4
q Slides from David Harris on transistor-level gate design. Available in PDF six to a page and in PDF two to a page , Reading: Chapter 1, Section 1.4.
q Intro to Layout, Design Rules. Available in PDF six to a page and in PDF two to a page, Reading: Textbook Chapter 1, section 1.5 (and Chapter 6), CAD book Chapter 5
q Intro to Verilog testbenches. Available in PDF six to a page and in PDF two to a page, Reading: Textbook Verilog appendix (Appendix A), CAD book Chapter 4, Verilog docuements linked from this class web site.
q Even more Layout (line of diffusion layout, Euler diagrams, stick diagrams). Available in PDF six to a page and in PDF two to a page, Reading: Textbook Chapter 5, section 5.3 in particular, CAD book Chapter 5.
q MOS Transistor Theory Available in PDF six to a page and in PDF two to a page, Reading: Chapter 2, 4.
q CMOS processing and fabrication. Available in PDF six to a page and in PDF two to a page, Reading: Chapter 3
q Logical Effort transistor sizing available in PDF six to a page and in PDF two to a page.
q Logical Effort slides from David Harris (the co-author of our textbook, and co-author of the Logical Effort book) available in PDF six to a page and in PDF two to a page.
q Verilog for Synthesis. available in PDF six to a page and in PDF two to a page.
q Lightening tour of Design Compiler and SOC Encounter. available in PDF six to a page and in PDF two to a page.
q Slides on datapaths (adders, shifters, register files, etc.) in PDF six to a page and two to a page. Reading Textbook Chapter 10
q A start-to-finish example of a small MIPS-like processor. Verilog, synthesis, place and route. In PDF six to a page and two to a page. Reading Textbook Section 1.7 and CAD book Chapter 13.
q Slide about memory subsystems - SRAM, DRAM, register files, etc. In PDF six to a page and two to a page. Reading Textbook Chapter 11.
q Chip assembly using the Cadence Chip Assembly Router (ccar), and I/O pads.In PDF six to a page and two to a page. Reading CAD book Chapter 12.
q VGA display design - circuits, and interface. In PDF six to a page and two to a page. You can get additional hints and information about aVGA controller from this project which is from a previous version of this class.
q Slides on pad cells and on finishing the chip for fabrication. In PDF six to a page and two to a page.
qThese aren't really slides from this class, but you might find them interesting. This is a talk I gave to the ELEAP (freshman engineering seminar) students. You can ignore the stuff at the beginning about the Computer Engineering program. The potentially interesting stuff is towards the end (starting at page 9) talking about data center power requirements. In PDF two to a page.
Week Class Schedule 8/25-27 Intro and transistor switch-level circuits 9/1-3 more transistor switch level circuits, intro to layout, design rules, and simple Verilog 9/8-10
more layout, line of diffusion, Euler paths 9/15-17 MOS transistor theory and behavior (Ken Stevens is filling in this week) 9/22-24 CMOS processing and fabrication 9/29-10/1 Logical effort transistor sizing and analysis 10/6-8 Verilog for synthesis, synthesis overview, review of CAD3 register layouts 10/13-15 No Class - Fall Break 10/20-22 Verilog for synthesis, Synopsys overview (synthesis), SOC Encounter overview (place and route) 10/27-29 Datapath circuits (adders, shifters, etc) 11/3-5 NO LECTURES - Sign up for scheduled group project proposal meetings during class time this week 11/10-12 MIPS example of a complete (small) system , Memory subsystems 11/17-19 MIDTERM EXAM on 11/17, chip assembly, I/O pads on 11/19
11/24 (no class 11/26) VGA circuits on 11/24 (Thanksgiving on 11/26) 12/1-3 NO LECTURES - Sign up for scheduled group design reviews during class time this week 12/8-10 Testing preview (CS/ECE 6712), student project presentations in class Tue 12/15
(finals week)Final project due
Grading Policy
Grading will be based on participation. Expected participation includes:
o Homework: Written homework will take the form of problem sets, project proposals, and other written work.
o Labs: Labs involve mask-layout design of cells that will be used in your semester project. We will use CAD tools from Cadence and Synopsys runing on linux in the CADE lab.
o Design Review: A short presentation on your project given to the class.
o Mid-term Exam: There will be one exam given sometime in the middle of the semester.
o Class Project: The class project will require the design of a small digital standard cell library that will then be used as a target library for a moderate sized chip design. Class members will join design teams for the implementation of the design. More details on the format of the final report will be available later in the semester.
o Graduate Students: Those taking the graduate level course will have additional requirements that include a more rigorous project or design flow and the review of two papers relating to VLSI from journals or conferences in the area. These could be related to the project being implemented.
Percentages for grades are as follows:
§ Labs (cell designs) & Homework: 40%
§ Design Review: 5%
§ Mid-term Exam: 15%
§ Project (design and report) 40%
Helpful Information
q Here's a link to a page with lots of VGA timing info. Note that this is "official timing" information, and most VGA displays are quite forgiving if you are consistent with your own timing.
q This page from the XESS company has some examples of VGA controllers targetted at their Xilinx-based boards. So, memory details would have to be finessed for custom chips, but the basics might be interesting. The appnote for the simple controller for the ancient XS-40 board is a good basic design, although it's in VHDL in the appnote...
q Here's a link to a site with information about interfacing to a PS/2 keyboard and mouse. It describes the timing interface and the communication protocol that keyboards and mice use to send data through that link. Note that PS/2 keyboards, for example, don't send ascii. They send "make codes" and "break codes" on key press and key release that encode which physical key has been pressed. You need to map those keys to the letters using those codes if you want ascii.
q Chapter one from Sutherland, Sproull, and Harris' book on Logic Effort is here in PDF. The website for the book is located here
q A document by Eric Marsman from
q A guide to basic electronics including MOS transistors: Appendix B from Contemporary Logic Design by Randy Katz. You don't need to know the sections on bipolar or diode logic. The MOS section is the most important.
q Errata (mistakes) in the class textbook,
q The SCN3M_SUBM SCMOS design rules from MOSIS, translated to microns, in PDF format, and in Word format.
q The official SCMOS Rev8 design rules at MOSIS
q A link to Reid Harrison's CS/EE 5720/6720 Analog VLSI class. They are also using the NCSU CDK and the SCMOS rules so you can find more information here including tutorials on analog simulation of designs built with the NCSU CDK, and a layout tutorial.
q Information on Chip Fabrication: MOSIS (MOS Implementation Service) home page
q LaTeX style files for producing IEEE-formatted two-column papers: A .cls style file with formatting information, a .bst bibliography style file, and a sample .tex file that demonstrates how it all should be used.
q A Microsoft Word example file that shows how to get an IEEE format in MS Word.
q A data sheet on the HM6264 8kX8 SRAM from the DSL lab kits. This is a good example of a generic SRAM that shows read and write protocols.
q Documentation from Tanner Research about their digital pads in PDF. We'll be using these pads for our chip designs.
q A page from Americn Microsemiconductor that has lots of tutorials on various semiconductor topics.
q Here's a paper that I wrote a few years ago that describes a simple stack based architecture similar to the transputer that might make a great project. Even if you don't use this exact architecture, stack-based machine make nice simple processor architectures for those wanting to do a processor project. You definitely don't have to do this as a self-timed processor! It's a perfectly good synchronous stack machine too.
q Here are a couple papers from the Journal of Solid State Circuits about latches and flip flops. These are just a couple examples, there are lots of papers about this! These papers analyze different latch and flip flop circuits for speed and power performance.
o Comparative Analysis of Master Slave Latches and Flip-Flops for High-Performance and Low-Power Systems by Vladimir Stojanovic and Vojin G. Oklobdzija
o New single-Clock CMOS LAtches and Flipflops with Improved Speed and Power Savings by Jiren Yuan and Christer Svensson
q Compact yet High-Performance (CyHP) Library for Short Time-to-Market with New Technologies by Nguyen Minh Duc and Takayasu Sakurai. This paper makes a case that a small (11 or 20 cells) library can perform almost as well as a 400 cell library when used with Synopsys design compiler and standard benchmarks.
Tool Information (Cadence, Synopsys, Verilog, etc. )
q Single-page reference sheet on Verilog syntax. This is the language used by the Verilog-XL simulator in Cadence. PDF format
q A Verilog Quick Reference guide (in Postscript)
q Another Verilog guide, this one is a lab from another class, but it talks about simulating Verilog code using the Verilog-XL simulator.
q Yet another Verilog guide. This one is an introduction to Verilog from Daniel C. Hyde at
q A set of documents from Synopsys that describe good Verilog coding style for synthesis. They are all in linked PDF. Open the Table of Contents and you should be able click on the chapters in that file to open up the chapters.
Note that these files are only accessable to CS/EE 5710/6710 studentsq A reference manual from Synopsys describing the Verilog synthesis engine.
Note that these files are only accessable to CS/EE 5710/6710 students
Reference Material
q David Hodges, Analysis and Design of Digital Integrated Circuits (3rd ed), McGraw Hill, 2004.
q Wayne Wolf, Modern VLSI Design (3rd ed), Prentice Hall, 2002.
q Jan M. Rabaey, Digital Integrated Circuits (2nd ed), Prentice Hall, 2003.
q Glasser and Doberpuhl, The Design and Analysis of VLSI Circuits, (most detailed circuit treatment), Addison-Wesley, 1985.
q Michael J. S. Smith, Application-Specific Integrated Circuits, (new, comprehensive, advanced level) Addison-Wesley, 1997.
q Hodges and
q Hennessy and Patterson, Computer Organization & Design - The Hardware/Software Interface, (3810 text) Morgan Kaufmann, 1994.
q IEEE Journal of Solid-State Circuits
q EEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
q IEEE International Solid-State Circuits Conference, 1954 -
q Advanced Research in VLSI, 1980-
q IEEE Custom Integrated Circuits Conference, 1979 -
q EE Times, Electronics, Computer Design, EDN...
Tutorials on the CAD tools
We'll be using CAD tools from Cadence and Synopsys this semester. These are "industrial strength" CAD tools and are the same tools that major chip makers use to build commercial chips. As such they are very powerful tools but they ar en't necessarily intuitive to use. They are very efficient tools for the power user, but they sometimes have a steep learning curve.
The following draft book chapters are in PDF format… They are draft chapters from a previous semester, but they should get you going on CAD1 and CAD2 until the book is in the bookstore. Note that they're only accessable from the .utah.edu domain.
q Chapter 2: Cadence Design Framework
q Chapter 3: Composer Schematic Capture
q Chapter 4: Verilog Simulation
q Chapter 5: Virtuoso Layout Editor
q Chapter 6: Spectre Analog Simulation