CS/EE 5830/6830
VLSI Architecture
Spring 2011
General Information
 Instructor: Erik Brunvand,
MEB 3142, 5814345
 Class: TTh, 5:15pm  6:35pm, MEB 3147 (SoC large conference room)
 Erik's Office Hours: TTh after class, whenever my
office door is open, or by appointment
 TA: Anand Venkat, Office Hours Monday 12:10p1:40p, Friday 11:00a12:30pin the CADE lab
 Prerequisites: CS/EE3700 (Digital Design) and CS3810 (Computer
Architecture) or equivalent are required.
CS/EE 6810 Advanced Architecture would
be great. CS/EE 5710/6710 (IC Design) equivalent is very helpful but not
required.
Students without VLSI experience can do projects related to FPGAs.
 Textbook:
Digital Arithmetic by Milos Ercegovac and Tomas Lang.
A list of known errata (mistakes) in the text
can be found here.
 There are two class mailing lists:

cs6830@list.eng.utah.edu is a list of everyone in the class. I'll use
this list to send important information to everyone in the class so
you need to add yourself to that list! You can add yourself to this
list and see archived messages at
https://sympa.eng.utah.edu/sympa. This list has been populated
with the email of all students who were preregistered for CS/EE
5830/6830. Note that this automatic processes used your
@utah.edu email address, so please make sure that you're reading
that email address or have that address forward email to the place you
do read your email.
Also note that there is only one class mailing list even through
there are four course numbers being used (CS5830, CS6830, EE5830,
EE6830.
 teachcs6830@list.eng.utah.edu
Email sent to this list will go to both the professor and the
TA. This is BY FAR the preferred method of asking questions! It lets
all the teaching staff see and respond to the questions. Please use
this email address unless you have very specific reasons for only
sending email to one person.
Important Information
Course Description
In general VLSI Archtitecture is a class that looks in depth at a particular
application domain and how that domain interacts with VLSI implementation. This
year we'll be looking at Arithmetic circuits and systems. We will look
in detail at arithmetic subsystems and do projects based on studying and
characterizing the behavior (speed, power, size, etc.) of various arithmetic
subsystems for VLSI.
Grading
Grading will be based on participation. Note that grad students
registered for 6830 will be expected to read and evaluate two
additional papers so the grading scale is slightly different for
6830. Expected participation includes:
 Homework and labs  Problems out of the book, design problems
using the CAD tools, circuit simulation and characterization problems
(40% for 5830, 35% for 6830)
 Choosing, reading, and evaluating two technical papers (10% for 6830)
 Midterm Exam (15%)
 Class Project  Much of your grade will be based on
participation in the class project based on the concepts studied in
the class. This project will involve building, evaluating,
characterizing, and exploring arithmetic circuits using
FPGAs or CMOS standard cells.(45% for 5830, 40% for
6830) Breakdown of these points will be as follows:
 Project Technical Paper (20%)
 Project final status (does it work?) (5%)
 Supporting documents (i.e. schematics and diagrams) (10% for
5830, 5% for 6830)
 Simulation and testing results (10%)
Notice that although this is a projectbased class, 20% of the total
grade is based on writing about your results! Plan now to spend to
spend some time preparing a nice final paper and report document!
For the final project, all team members will receive the same
grade. However, there will be a chance at the end of the semester for
all team members to confidentially evaluate the contribution made by
their teammates to the project. If there is enough evidence that a
team member did not contribute effectively to the project, I may
reduce that team member's project score to account for this.
There will be some additional assignments for CS/EE6830
students involving reading, summarizing, and possibly presenting
papers related to the subject of the course.
Digital VLSI Chip Design using Cadence and Synopsys CAD Tools
We'll be using CAD tools from Cadence and Synopsys this
semester. These are "industrial strength" CAD tools and are the same
tools that major chip makers use to build commercial chips. As such
they are very powerful tools but they aren't necessarily intuitive to
use. They are very efficient tools for the power user, but they
sometimes have a steep learning curve.
We'll mostly use the schematic capture and Verilog simulation portions of the tools. Individual projects may choose to use the integrated circuit layout portions, but this will not be required.
I've written a book about using the Cadence and Synopsys tools. It's not required for the course, but I think it's an extrememly useful reference when you use the tools (and cheap as textbooks go...). If you want to, you can purchase the book through Amazon or other online booksellers. I'll put the first few chapters online for this class. These are draft chapters, but they're very similar to the published chapters. Please respect these files and don't copy them or let them escape
out to the web. The chapters will be available only from the utah.edu
web domain.
You are, of course, also free to read the CAD tool documentation and learn
more right from the source. However, I encourage you to start with the Lab
Manual because I know that using the tools in this way works. If you
discover some new trick about using the tools, I'd love to hear about
it!
The following draft book chapters are in PDF format:


Here's a good chapter from another book
Chapter one from Sutherland, Sproull, and Harris' book on Logical Effort is here in PDF. The website for
the book is
here
Assignments
Review assignment. In PDF.
This assignment is a
selfassesment assignment. It won't be graded You should take
this exam and try to do it without looking at other course
material. If you can answer all the questions then you have the right
background for this course. If you can't, you will need to brush up on
some of your digital logic background! Please take this seriously! If
you have trouble with this exam, you will also have trouble with the
project!
Information about CADE electronic handin can
be found here in PDF
CAD1: Cadence Schematic Capture and Simulation, Due Tuesday, January 25th, 5:00pm
Note  if you've taken 6710 or 6720 this will be a total review, but please do
it anyway to make sure we're all using the same Cadence setup.
CAD2: Timing in Verilog/Spectre simulations
plus problems from Chapter 1. Due Tuesday, February 8th, 11:59pm
CAD3: Prefix adder design and measurement Due Tuesday, February 22nd, 11:59pm
CAD4: Reduction by rows and columns Due Thursday, March 3rd, 5:00pm
CAD5: Power measurement and multipliers Due Tuesday March 29. The AddTest.v testbench file can be found
here.
 CAD5 update! There have bene some reports that the AddTest.v benchmark doesn't have enough time between test vector application and test vector evaluation. I really thought 20ns would be plenty, but just to make sure that this isn't causing problems, I've made a new version that everyone should use. It's called AddTest100.v and has 100ns between tests. When uyou use this file, simulatino for 2000ns during mixed analogdigital simulation.
 The calculator in the new (v6) version of Spectre looks a little different from the one shown in the CAD book. Here is a document with some hints about using the new interface.
CAD6: Final Project. You can choose your own project or choose one of the projects
I've described. You should turn in a short (12 page) project proposal by Tuesday, April 12th. The final project is Due on Tuesday May 3rd.
Helpful Info
There's a lot of good info on the CS/EE 5710/6710
Digital VLSI class web site that you might want to look at.
Look in the Tool Information part of that web site for useful
info about Verilog, for example. There are some quick reference
guides and tutorials that can give you good information about Verilog
as a language.
Here's information about using VNC to
run the tools remotely courtesy of Mike Lodder from a few years
ago. Using VNC to display the
cade desktop through the network on your home machine is much faster than
direct X11 tunnelling of the Cadence tools to your desktop X server...
Slides
 Slides for lecture 1: intro, CMOS transistors circuits
Available in PDF
six to a page
and in PDF
two to a page,
Reading: None  background material...
 Slides for Chapter 1 of the text.
Available in PDF
six to a page
and in PDF
two to a page,
Reading: Chapter 1, Digital Arithmetic.
 Slides for Chapter 2 of the text on twooperand addition.
Available in PDF
six to a page
and in PDF
two to a page,
Reading: Chapter 2, TwoOperand Addition.
 Slides for Chapter 3 of the text on multioperand addition.
Available in PDF
six to a page
and in PDF
two to a page,
Reading: Chapter 3, MultiOperand Addition.
 Slides for Chapter 4 of the text on multiplication
Available in PDF
six to a page
and in PDF
two to a page,
Reading: Chapter 4, Multiplication
 Slides for Chapter 5 of the text on division
Available in PDF
six to a page
and in PDF
two to a page,
Reading: Chapter 5, Division
Additional Reading:
 Slides about Floating Point.
Available in PDF
Reading: Chapter 8.
 Slides about asynchronous arithmetic units. Available in PDF six to a page
and
two to a page.
 Selected papers related to asynchronous arithmetic:
 LowPower Operation Using
SelfTimed Circuits and Adaptive Scaling of the Supply Voltate by
Nielsen, Niessen, Sparsoe, and van Berkel
 A LowPower Asynchronous Datapath
for a FIR Filter Bank by Nielsen and Sparsoe
 Designing Asynchronous Circuits for
Low Power: An IFIR Filter Bank for a Digital Hearing Aid by Nielsen
and Sparsoe
 A CMOS VLSI Implementation of an
Asynchronous ALU by Garside
 An Asynchronous, Iterative
Implementation of the Original Booth Multiplication Algorithm, by
Efthymiou, Suntiamorntut, Garside, and Brackenbury
 SelfTimed
CarryLookahead Adders by Cheng, Unger, and Theobald
 Speculative
Completion for the Design of HighPerformance Asynchronous Dynamic
Adders by Nowick, Yun, Beerel, and Dooply
 The Design of a Low Power
Asynchronous Multiplier by Liu and Furber
 A ZeroOverhead SelfTimed
160ns 54b CMOS Divider by Williams and Horowitz (ISSCC version)
 A ZeroOverhead SelfTimed
160ns 54b CMOS Divider by Williams and Horowitz(JSSC version)
 Some papers related to "Quake 3" inverse square root (unrelated to other topics, but potentially interesting project topic):
 Grad students in
CS/ECE 6830  you should look for two papers on arithmetic circuit topics to read and review for this class. These papers can be papers that you read to prepare for your final project, or the might be separate papers that you read just for this assignment. You can select any papers you like on the general topic of arithmetic circuits, but you should pass at least their titles to me first so I can make sure they sound appropriate. You can select papers from the links above if you like, or find your own. I suggest looking in journals like JSSC (Journal of Solid State Circuits), TCAD (Transactions on CAD), TVLSI (Transactions on VLSI) and in conferences like ISSCC (International Solid State Circuits Conference), GLSVLSI (Great Lakes Symposium on VLSI), VLSI (International Conference on VLSI), ARVLSI (Advanced Research in VLSI), CICC (Custom Integrated Circuits Conference), and also in architecture conferences like ISCA, MICRO,and ICCD.
Lecture Plan
We'll basically follow the textbook in terms of subjects, although I
will likely bring in additional material for some topics. Listed here
is the general plan for the order in which we'll look at material, but
I don't have a good feel for how long we will need to spend on each
topic so I'm not going to try to put dates in the lecture
plan. Interspersed with the arithmetic topics will be lectures on
using the various CAD tools that you'll need for the assignments and
for the projects.
Arithmetic Circuit Topics
 Basic number representation and algorithms
 Basic fixedpoint number representation (unsigned numbers, signed
numbers, sign detection, conversion, bitextension)
 Basic Addition and subtraction (signed and unsigned)
 Range extension and arithmetic shifts
 Basic multiplication (signed and unsigned)
 Basic division (restoring and nonrestoring)
 Speeding up addition
 carryripple
 switched carryripple
 carryskip
 carry lookahead
 prefix adder
 carryselect and conditional sum
 selftimed carrycompletionsensing adders
 carrysave adders
 Multoperand addition
 bitarrays
 reduction by rows (adders) and by columns (counters)
 sequential implementation
 combinational implementation including piplined arrays
 Multiplication
 sequential multiplication with recoding
 combinational multiplication with recoding
 combinations of sequential/combinational styles
 multiply/accumulate (MAC)
 squarers and constant multiple multipliers
 Division by digit recurrence
 fractional division
 integer division
 quotient digit selection function
 Square root by digit recurrence
 recurrence and step
 overall algorithm and timing
 combination of division and square root
 integer square root
 resultdigit selection
 computation by iterative approximation
 reciprocal
 division
 square root
 Floating point arithmetic
 floating opint represenation
 roundoff modes and error analysis
 IEEE 754 standard
 fp addition
 fp multiplication
 fp division and square root
CAD tools and circuit topics (interspersed with arithmetic topics!)
 Basic transistor level design
 Cadence Composer schematic capture
 Behavioral and switchlevel simulation (Verilog)
 various simulators including Cadence VerilogXL, Synopsys VCS,
and Mentor Modelsim
 various timing models including switchlevel timing, behavioral
level timing, and SDF backannotation timing
 Analog simulation with spectre (Cadence) and nanosim (Synopsys)
 Circuit synthesis with Synopsys Design Compiler
 Arithmetic circuit synthesis with Synopsys Module Compiler
 FPGAbased timing simulation with Xilinx ISE and Modelsim