CS/ECE 3700 - Digital System Design
Spring 2012

Initial Lecture Plan

Please make sure to read the relevant sections in the book before the lectures!

• Tuesday, Jan 10: Intro, Electronics Review
• Thursday, Jan 12: Intro to switching circuits and logic, truth tables. Sections 2.1-2.5
  
  
• Tuesday, Jan 17: Logic gates, Sum of Products, Product of Sums, etc. Sections 2.6-2.9
• Thursday, Jan 19: Boolean function manipulation, Verilog intro. Sections 2.10-2.11
  
  
• Tuesday, Jan 24: More Boolean theorms and Verilog. Chapter 2
• Thursday, Jan 26: Gate Implementation. Sections 3.1-3.4
  
  
• Tuesday, Jan 31: More gate implementation. Sections 3.5-3.11
• Thursday, Feb 2: Intro to Karnaugh maps. Sections 4.1-4.4 (Erik is out of town...)
  
  
• Tuesday, Feb 7: More Karnaugh maps. Sections 4.5-4.8
• Thursday, Feb 9: More Karnaugh maps. Sections 4.5-4.8
  
  
• Tuesday, Feb 14: Quine-McCluskey tabular minimization Section 4.9
  
• Thursday, Feb 16: Number representation. Sections 5.1-5.2, Signed/unsigned numbers, addition. Sections 5.3-5.4
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• Tuesday, Feb 21: More adders, and Verilog for arithmetic. Sections 5.5-5.6
• Thursday, Feb 23: MID-TERM EXAM I covering Chapters 1-4 (Erik is out of town)
  
  
• Tuesday, Feb 28: Other number systems - floating point, BCD, etc. and ASCII. Sections 5.7-5.8
• Thursday, Mar 1: Combinational circuits - muxes, Shannon expansion, decoders, encoders. Sections 6.1-6.4
  
  
• Tuesday, Mar 6: Combinational Circuits and arithmetic comparisons. Section 6.5
• Thursday, Mar 8: Verilog for Combinational citcuits. Sections 6.6-6.7
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• Tuesday, Mar 13: Spring Break - No Class
• Thursday, Mar 15: Spring Break - No Class
  
  
• Tuesday, Mar 20: Sequential Circuits I - flip flops and latches. Sections 7.1-7.7
• Thursday, Mar 22: Sequential Circuits II - More flip flops and latches, plus counters, registers etc. Sections 7.8-7.11
  
  
• Tuesday, Mar 27: Verilog for sequential circuits. Sections 7.12-7.14
• Thursday, Mar 29: Finite State Machines I - 8.1-8.3
  
  
• Tuesday, Apr 3: Finite State Machines II - more examples
• Thursday, Apr 5: MID-TERM EXAM II covering chapters 5-7
  
  
• Tuesday, Apr 10: Finite State Machines III - using Verilog to describe finite state machines. Sections 8.4-8.9
• Thursday, Apr 12: Digital System Design I. Sections 10.1-10.2
  
  
• Tuesday, Apr 17: Digital System Design II - Examples. Sections 10.3-10.4
• Thursday, Apr 19: Digital System Design III - More examples...
  
  
• Tuesday, Apr 24: Future Directions - where do you go from here?
  
  
• Tuesday, May 1: 10:30a-12:30p FINAL EXAM. This final exam schedule is set by the University.