CS/ECE 3700 - Digital System Design
Spring 2010

"If you've ever opened up your computer to get all the pizza crumbs out, you probably noticed that there's nothing in there but a shiny green board covered with silver lines and lots of little black doodads. This class will attempt to teach you what those doodads are, how they work, and why it costs so much to fix when you spill stuff all over them." - Bill Richardson, Former 3700 TA A more formal definition of this class might be: The purpose of CS 3700 is to introduce you to the fundamental concepts of digital system theory and design. This includes techniques for defining and minimizing logic functions, design of combinational and sequential logic circuits, state diagrams, Mealy and Moore finite state machine models, design with MSI and LSI parts, design with Field Programmable Gate Arrays (FPGAs), and system controller design. By the end of the course you should be able to understand digital problem descriptions, design and optimize a solution, and build, test, and debug the resulting circuit.

Teaching staff

The instructor is Prof. Erik Brunvand.
Phone: 581-4345. Office: MEB 3142. Please use the teach-cs3700@list.eng.utah.edu mailing list to send email about the class.
Office Hours: Tuesday and Thursday after class, when my office door is open, or by appointment

Teaching assistants are Toren Monson (full time) and Steven Miller (half time)

Prerequisites

College Administrative Guidelines

Textbook

CAD Software

Class Mailing Lists

There are two important class mailing lists:

• cs3700@list.eng.utah.edu is a list of everyone in the class. I'll use this list to send important information to everyone in the class!  This list has been populated with the email of all students who were preregistered for CS/ECE 3700. Note that this automatic processes used your <uid>@utah.edu email address, so please make sure that you're reading that email address or have that address forward email to the place you do read your email. Also note that there is only one class mailing list even through there are two course numbers being used (CS3700 and ECE3700).
  
• teach-cs3700@list.eng.utah.edu Email sent to this list will go to both the professor and the TAs. This is BY FAR the preferred method of asking questions! It lets all the teaching staff see and respond to the questions. Please use this email address unless you have very specific reasons for only sending email to one person.

Meeting times

• Lectures: CS/EE 3700 lectures are on Tuesday and Thursday from 12:25-1:45 in WEB L101.
  
  
• Labs: NOTE: Do not attend your lab in the first week of class. Labs will start in the second week of class. All labs will be held in the School of Computing Student Digital Systems Lab (DSL) whih is MEB 3133.
• Students have been assigned to lab sections. Find your lab section here!
  
  

  Lab Session 2 TA:	Toren	Wednesday	1:25-2:45pm
  Lab Session 3 TA:	Toren	Wednesday	3:40-5:00pm
  Lab Session 4 TA:	Toren	Thursday	2:00-3:20pm
  Lab Session 5 TA:	Toren	Friday	9:40-11:00am
  Lab Session 6 TA:	Steven	Friday	1:30-3:00pm
  Lab Session 7 TA:	Steven	Thursday	5:30-7:00pm

Office hours

The TAs hold their general office hours in the DSL. The times are:

• Toren: Wednesday 2:45-3:40pm
• Steven: Monday 3:00-4:30pm

Grading policies

THERE IS NO PROVISION FOR TURNING IN LATE LABS OR ASSIGNMENTS

Grading will be based on the following:

• Homework and Lab Assignments: 35%
• Final Lab Project: 15%
• MidTerm Exam I: 15%
• MidTerm Exam II: 15%
• Final Exam: 20%

• Within 90% of the best student: Some sort of A
• Within 80% of the best student: Some sort of B
• Within 70% of the best student: Some sort of C
• Within 55% of the best student: D
• Below 50% scaled percentage: E

Assignments

• Homework #1, Electronics review, Due Thursday Jan 21, 5:00pm.
• Homework #2, Boolean Expressions and a little Verilog, Due Tuesday February 2nd, 5:00pm.
  • Here's the Boolean theorems sheet I showed in class
• Lab #1, Circuits and Lab Kits, Wiring Demo due in your lab during the week of February 1st, printed documentation due Friday, February 5th, 5:00pm.
  Additional materials for this lab:
  • An Introduction to the Lab Kits. A document that describes the lab kits, the components, the boards, and the procedures for wire wrapping. This includes some discussion of an old tool (Powerview) that we don't use any more, so ignore that part.
  • A tutorial introduction to the ISE tools. This introduces the ISE tools that you will be using for schematic capture, simulation, and eventually mapping to the Xilinx part. I recommend that you run through this tutorial FIRST before you start on Lab1!!!!
  • Another short tutorial that reminds you of the critical parts of starting a new project.
  • A zip file with the 3700 Lab Kit project. You should add parts from this project to your Lab1 project so that you can include lab kit components in your schematics. See the Lab1 for details.
  • A text file that lists all the ICs in the 3700 lab kits by number and gives a short description of what they are.
  • A directory that contains PDF versions of the full data sheets for the labkit chips Note that these may not be the exact brand of chips in the kits so the timings may be slightly different, but the functionality is the same.
• Homework #3, Transistor Circuits (Chapter 3), Due Friday Feb 12th, 5:00pm.
• Lab #2, Verilog and using the FPGA, printed parts due Friday Feb 12th, 5:00pm, Circuit demo due in your lab during the week of Feb 15.
  Additional materials for this lab:
  • A tutorial introduction to the ISE tools with Verilog. This introduces how to use the ISE tools with a Verilog source rather than a schematic source. It covers entering the Verilog, simulating the Verilog, assigning pins to the FPGA, synthesizing to the FPGA, and uploading the configuration to the XSA-50 board. I recommend that you run through this tutorial FIRST before you start on Lab2!!!!
  • You can find information about how the switches, LEDs, and other things are connected to the FPGA on the Xess board here:
    • The Xess XSA (FPGA board) pins assignments in an Excel spreadsheet.
    • The Xess XSA (FPGA board) pins assignments in PDF.
  • Additional XSA-50 board documentation is at the bottom of this web page...

Lecture Plan

Here's a link to an initial lecture schedule. Things will almost certainly drift a little, but here's my plan at least. Please make SURE that you read the appropriate sections in the book BEFORE the lecture!

• Four-to-a-page copies of slides from the electronics review, in PDF
• Introduction slides with basic course info: two to a page and six to a page, in PDF
• Toren's slides from Chapter 3, In PDF with annotations

Handouts and Other Useful Information

• Here's a list of errata (mistakes) in the book from the publisher's web site.
• PDF copy of another Electronics Review.
• Information about using Map Entered Variables (MEV) in Karnaugh maps. These are scanned from Fletcher's book An Engineering Approach to Digital Design. Note that these pages describe a slightly more complex version that involves don't cares. It's more common just to have variables on their own without added don't cares on the MEVs, so just look at the plain MEV stuff: Page 1, Page 2, Page 3, Page 4, Page 5, Page 6,

• Info about the lab kits...
  • This is a somewhat old file that introduces the lab kits. I wrote it a few years ago when we were sitll using a tool called Powerview. We aren't using that any more so you can ignore that part. There's still good information in here about the 7400-series parts, and how to wire them on the XST board.
  • A text file that lists all the ICs in the 3700 lab kits by number and gives a short description of what they are.
  • A directory that contains PDF versions of the full data sheets for the labkit chips Note that these may not be the exact brand of chips in the kits so the timings may be slightly different, but the functionality is the same.

• Info about the FPGA boards in the lab kits...
  • The Xilinx corporation website. This is the company that makes the FPGA that is used on our lab board.
  • The Xess corporation website. This is the company that makes the boards that we use in the lab.
  • The Xess XST (extender board) user's manual in PDF.
  • The Xess XSA (FPGA board) user's manual in PDF.
  • The Xess XSA (FPGA board) pins assignments in an Excel spreadsheet.
  • The Xess XSA (FPGA board) pins assignments in PDF.

• Verilog Information
  • Single-page reference sheet on Verilog syntax in PDF.
  • A multi-page Verilog quick reference sheet.
  • A longer Verilog Quick Reference guide in PDF
  • Yet another Verilog guide. This one is an introduction to Verilog from Daniel C. Hyde at Bucknell University. This guide is targeted at simulation.

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