CS/ECE 3700 - Digital System Design
Tuesday-Thursday, 12:25-1:45, WEB L101
Prof. Erik Brunvand
| "If you've ever opened up your computer to get all the pizza
crumbs out, you probably noticed that there's nothing in there but a
shiny green board covered with silver lines and lots of little
black doodads. This class will attempt to teach you what those
doodads are, how they work, and why it costs so much to fix when
you spill stuff all over them." |
- Bill Richardson, Former 3700 TA
|A more formal definition of this class might be:|
The purpose of CS 3700 is to introduce you to the
fundamental concepts of digital system theory and design. This
includes techniques for defining and minimizing logic functions,
design of combinational and sequential logic circuits, state
diagrams, Mealy and Moore finite state machine models, design with
MSI and LSI parts, design with Field Programmable Gate Arrays
(FPGAs), and system controller design. By the end of the course
you should be able to understand digital problem descriptions,
design and optimize a solution, and build, test, and debug the
Behind any engineering system is an efficient model that allows to analyze (and optimize) its characteristics. Digital circuits can be easily modeled using concepts such as Boolean algebra. Hence Boolean algebra is a fundamantal part of this course. This algebra allows to make Logical decisions, analyses and optimizations over a digital design so as to make it function correctly and robustly. This is something that you will learn in this course.
Secondly, this course is about designing systems. "Design" is really both a science and an art. The science is, of course, written in the books. But how to interpret that science and transform it into a functioning product is an art - something that you learn only by experience. Hence, this course will have a significant portion of design-work, both via HWs and Laboratory experiments. Finally, the course would be taught through a Computer-Aided Design (CAD) perspective.
The instructor is
Prof. Erik Brunvand.
Phone: 581-4345. Office: MEB 3142. Please use the email@example.com mailing list
to send email about the class.
Office Hours: Tuesday and Thursday after class, when my office door is open, or
Teaching assistants are TBA
CS 1410 (Intro to CS) or 2000 (Intro to Programming), and PHYCS 2220: Physics
for Scien. & Engineering II.
The purpose of the pre-reqs is to make sure that you have some basic programming background because we'll be using the Verilog hardware description language. This is a programming language for describing hardware that looks (at least superficially) like C. So, I'm assuming that you have some basic programming background so we won't have to go over basic programming concepts, and can jump right in to the specific features of Verilog.
The purpose of the Physics requirement is so that you will have seen basic electronics stuff: resistance, capacitance, current, voltage, Ohm's law, Kirchoffs laws, etc.
College Administrative Guidelines
The College of
Engineering Spring 2012 guidelines are here in PDF.
Fundamentals of Digital Logic with Verilog Design, 2nd edition, by
Stephen Brown and Zvonko Vranesic, c2008. Available at the University
Bookstore and at various places on the web.
We'll be using the free ISE WebPACK software from Xilinx for the
labs. Important! Version 10.1 SP3 is required for this class because newer versions do not have support for our Spartan2 FPGAs. We'll use this software for schematics, circuit and Verilog simulation,
Verilog synthesis, and mapping circuits to the Xilinx FPGAs. You can download a
free copy to your own PC at this Xilinx web
site. You'll have to register, but it doesn't cost anything. If you want to install this on your own machine make sure that you scroll to the bottom and get version 10.1 SP3. Also be aware that our Xilinx boards require a parallel port for programming, so if you have a machine without a parallel port (which is most modern machines...) then you'll be able to use the software for designing and simlulating your circuit, but you will have to come in to the lab to program the information onto your board.
Class Mailing Lists
There are two important class mailing lists:
- firstname.lastname@example.org is a list of
everyone in the class. I'll use this list to
send important information to everyone in the class!
This list has been populated with the email of all students who were preregistered for CS/ECE 3700. Note that this automatic processes used your <uid>@utah.edu email address, so please make sure that you're reading that email address or have that address forward email to the place you do read your email. Also note that there is only one class mailing list even through there are two course numbers being used (CS3700 and ECE3700).
Email sent to this list will go to both the professor and the TAs. This
is BY FAR the preferred method of asking questions! It lets
all the teaching staff see and respond to the questions. Please use this
email address unless you have very specific reasons for only sending email to
- Lectures: CS/EE 3700 lectures are on Tuesday and Thursday from
12:25-1:45 in WEB L101.
- Labs: NOTE: Do not attend your lab in the first
week of class. Labs will start in the second week of class.
will be held in the School of Computing Student Digital Systems Lab (DSL) which
is MEB 3133.
- NOTE We've made a few changes to the lab times.
- Lab Session Changes are in red
- Note that nobody is in Lab Session 3. If there are a few people who want to move, we'll open it up. But we need at least 5-6 people who want to move to make that happen.
|Lab Session 2
|Lab Session 3
|Lab Session 4
|Lab Session 5
|Lab Session 6
|Lab Session 7
Prof. Brunvand's hours are after class, whenever his
door is open, and by appointment in his office (3142 MEB).
The TAs hold their general office hours in the DSL. The times are:
- Paymon: Monday 2:00-4:00
- Leif: Tuesday 3:30-5:30
THERE IS NO PROVISION FOR TURNING IN LATE LABS OR ASSIGNMENTS
Grading will be based on the following:
Final point totals will be scaled so that the best student in the class has
100%. All students will be scaled by the that amount. Grade ranges will be:
- Homework and Lab Assignments: 35%
- Final Lab Project: 15%
- MidTerm Exam I: 15%
- MidTerm Exam II: 15%
- Final Exam: 20%
- Within 90% of the best student: Some sort of A
- Within 80% of the best student: Some sort of B
- Within 70% of the best student: Some sort of C
- Within 55% of the best student: D
- Below 50% scaled percentage: E
Cheating will not be tolerated! The School of Computing is adopting a "two strikes and you're out" policy. This means:
- The default penalty for cheating will be failure in the course. This counts as a strike.
- In gray areas, an instructor may apply a less severe penalty. This does not count as a strike.
- If you have two strikes, you will no longer be allowed to register for CS courses, or cross-listed courses taught by a CS professor.
A discussion of the cheating issue as it relates to this class can be found here
Official School of Computing policy on cheating: Given the unfortunate rise in cheatiing, the SoC faculty has decided to take a tougher stance in hopes of reversing things. In short - every instructor will define what they consider as cheating for each course. Starting now the default sanction for cheating is that the offender will be given a failing grade as the sanction. These sanctions will be recorded and kept in the SoC office in the student's personal file. After the second such sanction, the offending student will be permanently dropped from any SoC degree program and if they are in another non-SoC program they will be subsequently prohibited from taking any more CS classes.
Part of the process is that every current undergraduate CS or CE major, or SoC graduate student must turn in a form acknowledging that they have read the policy and understand the penalties involved. Fortunately you only need to do this once during your degree program.
So you need to read the policy: http://www.cs.utah.edu/internal/cheating_policy.pdf
And print and sign this form: http://www.cs.utah.edu/internal/SoC_ack_form.pdf
For CE undergraduates, the form needs to be turned into Arlene Arenaz (MEB 3313)
For CS undergraduates, the form needs to be turned into Vicki Jackson (MEB 3190)
For SoC graduate students, the form needs to be turned into Ann Carlstrom (MEB 3190)
Hand in hard-copy paper assignments in the box outside the School of Computing
front office (MEB 3190). Make SURE to put your name and your lab section
clearly on the front of the assignment. Partial credit is possible, but only if
we can understand what you did, and how you reached that conclusion.
- HW1 - Electronics Review Due Wednesay, Jan 18, 5:00pm
- HW2 - Truth tables and SOP/POS forms from Chapter 2, Due Wed Jan 25, 5:00pm
- I won't be doing this for all HWs, but some students are still waiting for their book.
So, here is a scanned section of the book that contains the problems from HW2 and HW3.
- HW3 - Boolean function manipulation and minimization from Chapter 2, Due Wed, Feb 1 at 5:00pm
- HW4 - CMOS transistor circuits and PLAs from Chapter 3, Due Wed, Feb 8 at 5:00pm
- HW5 - Boolean minimzation using Karnaugh maps from Chapter 4, Due Wed, Feb 15 at 5:00pm
- HW6 - Tabular minimization and cost functions from Chapter 4, Due Wed, Feb 22 at 5:00pm
- HW7 - Number representations and arithmetic circuits from Chapter 5, Due Fri, Mar 9 at 5:00pm
- HW8 - Combinational Circuits from Chapter 6, Due Wed, Mar 28 at 5:00pm
- HW9 - Flip Flops from Chapter 7, Due Wed, Apr 11 at 5:00pm
- Lab1 - Intro to the Lab Kit and switch/LED wiring. Demo during your lab 2/1-2/3
- Lab2 - Verilog for combinational circuits. Demo during your lab 2/15 - 2/17
- Lab3 - Verilog/Schematic mix and adder circuits. Demo during your lab 3/7 - 3/9 (updated dates!)
- Lab4 - Arithmetic comparison. Verilog simulation only - documentation due Friday March 23
- Lab5 - Finite State Machine. Demo during your lab 4/4 - 4/6
- Lab6 - T-bird tail lights. Demo during your lab 4/11 - 4/13
- Lab7 - Final Digital System Lab: UART. Demo during TA hours on M-T 4/23 or 4/24 This lab may be done in teams of two if you like.
Here's a link to an initial lecture
schedule. Things will almost certainly drift a little, but here's my plan
at least. Please make SURE that you read the appropriate sections in the book
BEFORE the lecture!
- Intro slides in PDF 2 to a page and 6 to a page
- Four-to-a-page copies of slides from the electronics review, in PDF
- Our first midterm which covers topics from Chapters 1-4 will be on Thursday 2/23 during class
- The second midterm will cover material from Chapters 5-7, and will be Thursday, April 5
- The final will cover material from all chapters, but be focused primarily on finite state machine design and implementation
- The final will be on Tuesday, May 1st from 10:30-noon in our regular classroom.
- Here's a list of topics for the final
- I suggest the following problems from the book as study problems: 8.1, 8.2, 8.5, 8.6, 8.9 8.11, 8.20, 8.21, 8.22, 8.29, 8.34
- I'll go over these problems in class on Tuesday, 4/24 as a study session for the final.
Handouts and Other Useful Information
- Here's a list of errata (mistakes) in the book
from the publisher's web site.
- PDF copy of another Electronics Review.
- Information about using Map Entered Variables (MEV) in Karnaugh
maps. These are scanned from Fletcher's book An Engineering Approach
to Digital Design. Note that these pages describe a slightly more
complex version that involves don't cares. It's more common just to
have variables on their own without added don't cares on the MEVs, so
just look at the plain MEV stuff:
- Info about the lab kits...
- Info about the ISE tool...
- Info about the FPGA boards in the lab kits...
- Verilog Information
ADA Statement: The University of Utah
ECE Department and School of Computing seek to provide equal access to its
programs, services and activities for people with disabilities. If you will
need accommodations in this class, reasonable prior notice needs to be given to
the instructor and to the Center for Disability Services, 162 Olpin Union Bldg,
581-5020 (V/TDD) to make arrangements for accommodations. This information is
available in alternative format with prior notification.