VLSI/Circuit CAD Tools in the College of Engineering |
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VLSI and digital/analog circuit CAD tools in the College of Engineering are available on CADE and CS machines. They are automounted such that you always get the right binaries for the machine type you're on. Because these tools often have complex environment requirements (paths, variables, etc.) we've put these startup constraints into setup files for each tool group. In addition, there are wrappers that source these setups in a new shell then call the tool. It is highly recommended that you use these wrappers, or at least these startup scripts, to use the tools. We know that they work with these configurations. If you need something different, you should probably start with the setup script as a starting point for your own customizations.
All tool startup wrappers are in /uusoc/facility/cad_common/local/bin/ under the following directories based on the tool release, unless otherwise described:
The setup scripts called by these wrappers are in /uusoc/facility/cad_common/local/setups. The tool versioning is beginning to be implemented here as well, through the directory F06 to get the old programs and scripts. (Better organization is coming.)
Documentation scripts for the tools are in the same directory as the startup wrappers. The documentation scripts normally start with a uu- prefix.
Many tools are now being converted to using the tcl scripting
language. The following web page is a good reference for getting up
to speed programming in the tcl language:
http://www.tcl.tk/man/tcl8.5/tutorial/tcltutorial.html
The tools are currently maintained by operators in the CADE Lab, and Erik Brunvand in the School of Computing, and to a lesser extent Ken Stevens in the Electrical and Computer Engineering Dept. This file was last modified on .
Cadence |
All Cadence tools are loaded in /uusoc/facility/cad_tools/Cadence into a directory named for the release version. Symbolic links are then made to those release directories so that if you follow the symbolic link you will always get the most current recommended release. If you need a different release, you can always modify the setups to suit your particular needs. Setup files are setup-ncsu for a version with the NCSU tech files (for MOSIS VLSI technologies) or setup-cadence for a base Cadence setup. Wrappers are available for the commonly used programs and are described below. The Cadence documentation can be viewed here. |
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Release Version |
Tools |
Installed |
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IC Tools link: IC |
IC 6.1.4 |
Design Framework II |
Linux |
| Notes: |
These tools are all called from the Design Framework. You can start up the design framework using the following wrappers: cad-ncsu for the version with the NCSU technology libraries There are tutorials for Virtuoso, Composer, Diva and CSI on the CS/EE 6710 website. There are no local tutorials for Dracula or Cadence SPICE |
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| link: ASSURA | ASSURA 3.1.3 |
Assura DRC Assura LVS Assura physical verification |
Linux |
| Notes: | Assura is installed, but we don't currently have the DRC and LVS files for Assura loaded. In principle we can convert the Diva DRC and LVS files for use with Assura for the NCSU technologies. There are two versions of Assura - one for CDB (Cadence Database) designs, and one for ICOA (Open Access database) designs. Currently the IC classes use CDB, but we should probably move to ICOA in the future...
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Chip assembly tools link: ICC |
ICC 11.2.41 |
Cadence Chip Assembly Router | Linux |
| Notes: | This tool (ccar) is called from Virtuoso-XL in our flow. There is no stand-alone wrapper. See the tutorial on the CS/EE 6710 website for details. |
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Analog simulation link MMSIM |
MMSIM 6.0 |
Spectre analog circuit simulator Ultrasim full chip simulator Spectre RF simulation option |
Linux |
| Notes: | Spectre is the main analog simulator used in our class flow. We generally use it from the Affirma Analog framework (called from Virtuoso). So, this is called from the IC tools, and there is no stand-alone wrapper. See the tutorials on the CS/EE 6710 website. |
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HDL Simulators link:LDV |
LDV 5.1 |
NC-Verilog simulator NC-VHDL simulator NC-Sim mixed language simulator Verilog-XL Incisive unified simulator Affirma analog simulation environment |
Linux |
| Notes: | These simulators can be called from the IC tools (from the Composer schematic tool in particular), or stand-alone. For Composer integration see the tutorials on the CS/EE 6710 website. To call stand-alone, source the cadence setup script (either setup-cadence or setup-ncsu to get the NCSU tech file) and then execute with verilog for verilog-xl, ncvlog for nc-verilog, or ncvhdl for nc-vhdl. Verilog-XL is interpreted and was for years (and still is for some) the "sign-off" version of Verilog simulation. the NC versions compile a fast simulator from your HDLcode and so take a little longer to start up, but result in a faster simulation. I don't know what exactly Incisive is. We have a license for the newer versions in the IUS5.4 release and should upgrade to that soon... |
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Place and Route link: SOC |
SOC 9.1 |
SOC Encounter Global Physical Synthesis (GPS) Envisia Physically Knowledgeable Synthesis (PKS) |
Linux |
| Notes: | These are the currently supported place and route tools that replace Silicon Ensemble, called with wrapper cad-soc. The pks_shell is Cadence's version of HDL synthesis (i.e. does the same thing as dc_shell from Synopsys). Documentation on SoC can be obtained here. |
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3D RC extraction link: none yet |
SEV 3.2 | Fire & Ice QX 3D RC extractor | Linux |
| Notes: | This is the "sign off" RC extractor that is used by SOC Encounter place and route. We have it installed, but haven't used it and don't have it configured. We also don't have capacitance tables at the moment that are required by the tool | ||
Signal Integrity Analysis, and library characterization link: none yet |
TSI 4.1 | CeltIC crosstalk analyzer PacifIC static noise analyzer SignalStorm Nanometer Delay Calculator SignalStorm library characterizer |
Linux |
| Notes: | The signal integrity analyzers are linked in with the SOC Encounter tools, but we haven't used them yet. SignalStorm is a tools used to generate characterizations for standard cell libraries. It seems like a very useful tool, but we haven't used it yet. |
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PCB tools link: none yet |
SPB 15.2 | Allegro PCB designer Allegro PCB Signal Integrity analysis Orcad PCB designer Orcad LayoutPlus |
Linux |
| Notes: | Tools for designing printed circuit boards. We haven't used them yet. | ||
| Various... | PAS 3.0 | Pcell generator | |
| Neockt 3.2 | NeoCircuit Design for Manufacturability |
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| Neocell 3.4 | NeoCell analog physical synthesis | ||
| SEV 4.1 | Voltagestorm power analyzer | ||
| IUS 5.3 | FormalCheck model checker | ||
| CONFRML 5.0 | Conformal Ultra | ||
| RC 4.2 | Encounter RTL Compiler Ultra | ||
| VSDE 4.1 | Virtuoso Specification Driven Environment |
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| Notes: | I don't know much about these tools other than their names. They are (mostly) installed, but no wrappers or any other scripts have been generated. You're on your own for these at the moment! | ||
Synopsys |
All Synopsys tools are loaded in /uusoc/facility/cad_tools/Synopsys into a directory named for the release version. Symbolic links are then made to those release directories so that if you follow the symbolic link you will always get the most current recommended release. If you need a different release, you can always modify the setups to suit your particular needs. Setup file is setup-synopsys. The Synopsys documentation can be viewed by running uu-sold. |
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Release Version |
Tools |
Installed |
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Core synthesis tools link: syn |
D-2010.03-SP2 |
DC Ultra (Design Compiler Ultra)
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Linux |
| Notes: |
Design Compiler Ultra is Synopsys' main synthesis product. It can be called as a shell with syn-dc, or or syn-dv for design vision. Design vision is the currently supported GUI for Design Compiler. The new XG version of design compiler uses tcl syntax for command scripting. Documentation for the XG version and the tcl interface are in the dcxg.pdf document. One can also a utility from Synopsys called dc-transcript that converts the old dc_shell script to the new tcl script. The program can be found in the path /uusoc/facility/cad_common/Synopsys/ under directory SYN-F06/OSVER/syn/bin/dc-transcript where OSVER is replaced, based on your operating system, with linux, amd64, suse32, suse64, sparcOS5, or sparc64. DesignWare is a collection of pre-designed datapath circuits (see the tutorial and the .synopsys_dc.setup file for details). Library compiler (syn-lc) converts .lib files that describe target libraries into synopsys database files (.db). Module compiler (syn-mc) is a specialty datapath compiler. There are tutorials for most of these tools on the CS/EE 6710 website.
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Analog Simulation link: ns |
ns-W- 2004.12-SP2 |
NanoSim | Linux |
| Notes: | NanoSim is Synopsys' fast analog simulator. It is "spice-like" but much faster (with slightly less accuracy). Binu and Ali used to use this a lot, but it hasn't been used in classes so there are no tutorials available. There is a (not tested) syn-ns wrapper available. | ||
Timing analysis link: pt |
pt_vX- 2005.06-SP2 |
PrimeTime |
Linux |
| Notes: | Synopsys' static timing analysis tool. No tutorials available at the moment, but there is a syn-pt wrapper. | ||
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HDL Simulation link: vcs |
vcs_mx7.2 |
vcs HDL simulator | Linux |
| Notes |
Fast Verilog and VHDL mixed simulation A syn-vcs wrapper is available, but there are no tutorials. Some students (Binu and Ali?) used to use this a lot. |
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Circuit simulator link: hspice |
C-2009.09-SP1 |
hspice | Linux |
| Notes |
Analog circuit simulator (SPICE). The hspice wrapper calls a setup script and runs hspice. There is a gui version provided by Synopsys, but we don't have any scripts set up for that. The best SPICE documentation we have is from Cadence in the file hspiceref.pdf. We don't have any tutorials set up for hspice. |
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Waveform viewer link: Cosmos |
B-2008.09-SP2 |
Cosmos Scope | Linux |
| Notes |
Spice waveform viewer and manipulator. A syn-cscope wrapper is available, but there are no tutorials. |
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Mostly what we use from Synopsys is Design Compiler, but they have a lot more tools available This is a complete list of Synopsys tools we have a license for... I've annotated this list with what I think the version is in our license file. If you need any of the tools that are not installed, we can install them, but you'll have to help with wrappers and setup scripts! |
Various |
ApolloAdv Clock Management Op. 2004.12? ApolloAdv Timing Driven Op. Apollo-Clock Skew Management ApolloTiming Driven Op Apollo-VDSM Place & Route + 5 MW Astro Basic UDSM Place & Route 2004.12 Astro Express Tim. Closure Op. Astro Pro Option Astro Rail Astro XTalk avanWaves for Unix 20005.03? BDC for NanoSim 2004.12? BSD Compiler ?? CHV-Addtnl. ChipViewer 2--3.03? CosmosLE Cosmos-V-2004.06 CosmosSE Cosmos-V-2004.06 DC Ultra syn_vW-2004.12-SP4 Design Analyzer syn_vW-2004.12-SP4 Design Vision syn_vW-2004.12-SP4 DesignWare AMBA SystemC Lib. 2004.09? DesignWare Developer dwd_2002.05 DesignWare Library syn_vW-2004.12-SP4 DFT Compiler 2004.12? Formality 2005.03? FPGA Compiler II 2003.09 (obsolete - use DC Ultra) HDL Compiler Verilog 2004.06? Hercules 2004.12? Hercules DP/MT Add-on HSPICE Link-3rd Party Link 2004.12? HSPICE w/Cosmos-Scope Integrator/Falcon Framework 2004.12? JupiterXT 2004.12? LEDA Checker 2004.06? LEDA Specifier Library Compiler syn_vW-2004.12-SP4 LSI NDL Interface 2004.12? Milkyway C-API Dev. 2005.03? 2004.12? Milkyway Environment & RunTime C-API Module Compiler syn_vW-2004.12-SP4 NanoSim ns-W-2004.12-SP2 Pathmill 2004.12? Physical Compiler ??? Power Compiler ??? PrimePower 2004.12? PrimeTime pt_vX-2005.06-SP2 PrimeTime SI Add-on pt_vX-2005.06-SP2 RailMill-XP 2003.03? Saber Component Library Add-On 2004.12? Saber Harness Saber Inspecs Add-On Saber Simulator Saber Sketch Saber Template Library Add-On Star-MTB 2004.12? Star-MTB Basic Star-RCXT System Studio ??? System Studio ECC Model Library System Studio Filter Design Tools Taurus Process Atomistic TCAD-Raphael ??? TCAD-Taurus Device 3D Op. TCAD-Taurus Modeling Environment TCAD-Taurus Process 3D Op. TCAD-Taurus-DFM Option TCAD-Taurus-Medici TCAD-Taurus-TSuprem4 TDL Interface 2004.12? TetraMAX ATPG 2004.12? TetraMAX DSM Test TetraMAX IddQ Test VCS MX vcs_mx7.2 Vera Developers Kit vera-6.2.8-linux2.2.14 VHDL Compiler 2004.12? |
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Mentor |
All Mentor tools are loaded in /uusoc/facility/cad_tools/Mentor into a directory named for the release version. Setup file is setup-mentor |
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Release Version |
Tools |
Installed |
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HDL Simulation
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v6.3 |
Modelsim SE simulator (also called Modeltech)
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Linux, Windows |
| Notes: |
Mentor's flagship HDL (mixed VHDL and Verilog, or System-C) simulator. It is launched with the modelsim command. There is a Windows version as well as Linux. This tool is also integrated with the Xilinx ISE/Webpack FPGA tools. Documentation for Modelsim can be obtained for version 5 here, and for version 6 here. |
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Other installed tools from Mentor |
FPGA Advantage v6.2 (FPGA design tool) HDL Designer (graphical HDL front end) Precision RTL synthesis (FPGA) Precision Physical Synthesis (FPGA) Leonardo Spectrum (ASIC synthesis) Design for Test PCB Expedition |
Linux, Windows | |
| Notes: |
We haven't used the Mentor tools much. These tools are installed, but there are no wrappers or tutorials available at the moment. |
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Coming soon from Mentor? |
Eldo (analog sim) |
Linux, Windows | |
| Notes: |
There's been talk about getting the DSM IC tools from Mentor. If we do, these tools will be included in that suite |
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Xilinx |
The Xilinx ISE/Webpack tools are installed in the SoC PC lab and in the student Digital Systems Lab primarily for use in CS/EE 3700 and 3710 where they are used with the Xilinx-based proto boards from Xess. |
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Release Version |
Tools |
Installed |
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FPGA design synthesis, mapping, and bitstream generation
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Can't remember... |
Xilinx ISE WebPack tools
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Windows |
| Notes: | We use the free WebPack tools in the DSL and the PC labs so that the version that the students can download and use on their own PCs will be the same as the lab version.
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ASYNC |
We have several asynchronous synthesis and verification tools that we have installed for all to use. The async root directory is /uusoc/facility/cad_tools/Async partition. To use the tools you will need to include /uusoc/facility/cad_tools/Async/bin in your search path. Documentation is in the doc subdirectory, and examples are in the examples subdirectory. |
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RELEASE VERSION |
Tools |
Installed |
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3D synthesis
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3.13 |
3D Asynchronous State Machine Synthesis
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Linux |
| NOTES: | This is the synthesis system based on multiple input change Burst-Mode methodology developed by Stevens at HP and implemented by Yun and Nowick at Stanford. This uses state machine specifications and produces two level logic that is usually very fast and efficient. However it relies on the fundamental mode timing assumption.
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